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Add dma::Reset

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scawful
2024-04-23 14:02:58 -04:00
parent 3eb7743dee
commit 265742f67c
2 changed files with 28 additions and 0 deletions
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27
src/app/emu/memory/dma.cc
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@@ -14,6 +14,33 @@ static const int bAdrOffsets[8][4] = {{0, 0, 0, 0}, {0, 1, 0, 1}, {0, 0, 0, 0},
static const int transferLength[8] = {1, 2, 2, 4, 4, 4, 2, 4}; static const int transferLength[8] = {1, 2, 2, 4, 4, 4, 2, 4};
void Reset(MemoryImpl* memory) {
auto channel = memory->dma_channels();
for (int i = 0; i < 8; i++) {
channel[i].bAdr = 0xff;
channel[i].aAdr = 0xffff;
channel[i].aBank = 0xff;
channel[i].size = 0xffff;
channel[i].indBank = 0xff;
channel[i].tableAdr = 0xffff;
channel[i].repCount = 0xff;
channel[i].unusedByte = 0xff;
channel[i].dmaActive = false;
channel[i].hdmaActive = false;
channel[i].mode = 7;
channel[i].fixed = true;
channel[i].decrement = true;
channel[i].indirect = true;
channel[i].fromB = true;
channel[i].unusedBit = true;
channel[i].doTransfer = false;
channel[i].terminated = false;
}
memory->set_dma_state(0);
memory->set_hdma_init_requested(false);
memory->set_hdma_run_requested(false);
}
uint8_t Read(MemoryImpl* memory, uint16_t adr) { uint8_t Read(MemoryImpl* memory, uint16_t adr) {
auto channel = memory->dma_channels(); auto channel = memory->dma_channels();
uint8_t c = (adr & 0x70) >> 4; uint8_t c = (adr & 0x70) >> 4;

1
src/app/emu/memory/dma.h
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@@ -12,6 +12,7 @@ namespace emu {
namespace memory { namespace memory {
namespace dma { namespace dma {
void Reset(MemoryImpl* memory);
void HandleDma(SNES* snes, MemoryImpl* memory, int cpu_cycles); void HandleDma(SNES* snes, MemoryImpl* memory, int cpu_cycles);
void WaitCycle(SNES* snes, MemoryImpl* memory); void WaitCycle(SNES* snes, MemoryImpl* memory);