Update Apu class
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@@ -31,10 +31,21 @@ void Apu::Init() {
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}
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void Apu::Reset() {
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clock_.ResetAccumulatedTime();
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spc700_.Reset(true);
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dsp_.Reset();
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romReadable = true;
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ram.clear();
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rom_readable_ = true;
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dsp_adr_ = 0;
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cycles_ = 0;
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memset(in_ports_, 0, sizeof(in_ports_));
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memset(out_ports_, 0, sizeof(out_ports_));
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for (int i = 0; i < 3; i++) {
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timer_[i].cycles = 0;
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timer_[i].divider = 0;
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timer_[i].target = 0;
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timer_[i].counter = 0;
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timer_[i].enabled = false;
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}
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}
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void Apu::Update() {
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@@ -69,18 +80,18 @@ void Apu::Cycle() {
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// handle timers
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for (int i = 0; i < 3; i++) {
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if (timer[i].cycles == 0) {
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timer[i].cycles = i == 2 ? 16 : 128;
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if (timer[i].enabled) {
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timer[i].divider++;
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if (timer[i].divider == timer[i].target) {
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timer[i].divider = 0;
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timer[i].counter++;
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timer[i].counter &= 0xf;
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if (timer_[i].cycles == 0) {
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timer_[i].cycles = i == 2 ? 16 : 128;
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if (timer_[i].enabled) {
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timer_[i].divider++;
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if (timer_[i].divider == timer_[i].target) {
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timer_[i].divider = 0;
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timer_[i].counter++;
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timer_[i].counter &= 0xf;
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}
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}
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}
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timer[i].cycles--;
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timer_[i].cycles--;
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}
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cycles_++;
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@@ -96,10 +107,10 @@ uint8_t Apu::Read(uint16_t adr) {
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return 0;
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}
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case 0xf2: {
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return dspAdr;
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return dsp_adr_;
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}
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case 0xf3: {
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return dsp_.Read(dspAdr & 0x7f);
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return dsp_.Read(dsp_adr_ & 0x7f);
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}
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case 0xf4:
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case 0xf5:
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@@ -107,20 +118,20 @@ uint8_t Apu::Read(uint16_t adr) {
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case 0xf7:
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case 0xf8:
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case 0xf9: {
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return inPorts[adr - 0xf4];
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return in_ports_[adr - 0xf4];
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}
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case 0xfd:
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case 0xfe:
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case 0xff: {
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uint8_t ret = timer[adr - 0xfd].counter;
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timer[adr - 0xfd].counter = 0;
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uint8_t ret = timer_[adr - 0xfd].counter;
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timer_[adr - 0xfd].counter = 0;
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return ret;
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}
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}
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if (romReadable && adr >= 0xffc0) {
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if (rom_readable_ && adr >= 0xffc0) {
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return bootRom[adr - 0xffc0];
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}
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return aram_.read(adr);
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return ram[adr];
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}
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void Apu::Write(uint16_t adr, uint8_t val) {
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@@ -130,51 +141,51 @@ void Apu::Write(uint16_t adr, uint8_t val) {
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}
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case 0xf1: {
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for (int i = 0; i < 3; i++) {
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if (!timer[i].enabled && (val & (1 << i))) {
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timer[i].divider = 0;
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timer[i].counter = 0;
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if (!timer_[i].enabled && (val & (1 << i))) {
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timer_[i].divider = 0;
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timer_[i].counter = 0;
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}
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timer[i].enabled = val & (1 << i);
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timer_[i].enabled = val & (1 << i);
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}
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if (val & 0x10) {
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inPorts[0] = 0;
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inPorts[1] = 0;
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in_ports_[0] = 0;
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in_ports_[1] = 0;
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}
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if (val & 0x20) {
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inPorts[2] = 0;
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inPorts[3] = 0;
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in_ports_[2] = 0;
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in_ports_[3] = 0;
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}
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romReadable = val & 0x80;
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rom_readable_ = val & 0x80;
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break;
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}
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case 0xf2: {
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dspAdr = val;
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dsp_adr_ = val;
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break;
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}
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case 0xf3: {
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if (dspAdr < 0x80) dsp_.Write(dspAdr, val);
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if (dsp_adr_ < 0x80) dsp_.Write(dsp_adr_, val);
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break;
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}
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case 0xf4:
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case 0xf5:
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case 0xf6:
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case 0xf7: {
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outPorts[adr - 0xf4] = val;
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out_ports_[adr - 0xf4] = val;
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break;
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}
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case 0xf8:
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case 0xf9: {
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inPorts[adr - 0xf4] = val;
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in_ports_[adr - 0xf4] = val;
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break;
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}
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case 0xfa:
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case 0xfb:
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case 0xfc: {
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timer[adr - 0xfa].target = val;
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timer_[adr - 0xfa].target = val;
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break;
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}
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}
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aram_.write(adr, val);
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ram[adr] = val;
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}
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uint8_t Apu::SpcRead(uint16_t adr) {
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@@ -56,8 +56,8 @@ typedef struct Timer {
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*/
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class Apu {
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public:
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Apu(MemoryImpl &memory, AudioRam &aram, Clock &clock)
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: aram_(aram), clock_(clock), memory_(memory) {}
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Apu(MemoryImpl &memory, Clock &clock)
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: clock_(clock), memory_(memory) {}
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void Init();
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void Reset();
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@@ -73,34 +73,22 @@ class Apu {
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uint8_t Read(uint16_t address);
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void Write(uint16_t address, uint8_t data);
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// Called upon a reset
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void Initialize() {
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spc700_.Reset();
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dsp_.Reset();
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}
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void UpdateClock(int delta_time) { clock_.UpdateClock(delta_time); }
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auto dsp() -> Dsp & { return dsp_; }
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uint8_t inPorts[6]; // includes 2 bytes of ram
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uint8_t outPorts[4];
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// Port buffers (equivalent to $2140 to $2143 for the main CPU)
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uint8_t in_ports_[6]; // includes 2 bytes of ram
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uint8_t out_ports_[4];
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private:
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// Constants for communication
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static const uint8_t READY_SIGNAL_0 = 0xAA;
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static const uint8_t READY_SIGNAL_1 = 0xBB;
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static const uint8_t BEGIN_SIGNAL = 0xCC;
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// Port buffers (equivalent to $2140 to $2143 for the main CPU)
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uint8_t ports_[4] = {0};
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Timer timer[3];
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Timer timer_[3];
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uint32_t cycles_;
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uint8_t dspAdr;
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bool romReadable = false;
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uint8_t dsp_adr_;
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bool rom_readable_ = false;
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std::vector<uint8_t> ram = std::vector<uint8_t>(0x10000, 0);
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// Member variables to store internal APU state and resources
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AudioRam &aram_;
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Clock &clock_;
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MemoryImpl &memory_;
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@@ -109,8 +97,8 @@ class Apu {
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[&](uint16_t adr) { return SpcRead(adr); },
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[&](bool waiting) { SpcIdle(waiting); },
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};
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Dsp dsp_{aram_};
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Spc700 spc700_{aram_, callbacks_};
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Dsp dsp_{ram};
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Spc700 spc700_{callbacks_};
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};
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} // namespace audio
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