Add CMP, COP, DEC, EOR, update SNES and Memory
This commit is contained in:
scawful
@@ -67,6 +67,22 @@ uint8_t CPU::FetchByteDirectPage(uint8_t operand) {
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return fetchedByte;
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}
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void CPU::Run() {
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while (true) {
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// Fetch the next opcode from memory at the current program counter
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uint8_t opcode = memory.ReadByte(PC);
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// Increment the program counter to point to the next instruction
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PC++;
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// Execute the instruction corresponding to the fetched opcode
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ExecuteInstruction(opcode);
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// Optionally, handle interrupts or other external events
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HandleInterrupts();
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}
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}
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void CPU::ExecuteInstruction(uint8_t opcode) {
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// Update the PC based on the Program Bank Register
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PC |= (static_cast<uint16_t>(PB) << 16);
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@@ -262,11 +278,11 @@ void CPU::ExecuteInstruction(uint8_t opcode) {
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break;
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case 0x50: // BVC Branch if overflow clear
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// BVC();
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BVC(ReadByte(PC));
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break;
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case 0x70: // BVS Branch if overflow set
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// BVS();
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BVS(ReadByte(PC));
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break;
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case 0x18: // CLC Clear carry
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@@ -286,49 +302,49 @@ void CPU::ExecuteInstruction(uint8_t opcode) {
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break;
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case 0xC1: // CMP DP Indexed Indirect, X
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// CMP();
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CMP(DirectPageIndexedIndirectX());
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break;
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case 0xC3: // CMP Stack Relative
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// CMP();
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CMP(StackRelative());
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break;
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case 0xC5: // CMP Direct Page
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// CMP();
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CMP(DirectPage());
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break;
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case 0xC7: // CMP DP Indirect Long
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// CMP();
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CMP(DirectPageIndirectLong());
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break;
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case 0xC9: // CMP Immediate
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// CMP();
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CMP(Immediate(), true);
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break;
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case 0xCD: // CMP Absolute
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// CMP();
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CMP(Absolute());
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break;
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case 0xCF: // CMP Absolute Long
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// CMP();
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CMP(AbsoluteLong());
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break;
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case 0xD1: // CMP DP Indirect Indexed, Y
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// CMP();
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CMP(DirectPageIndirectIndexedY());
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break;
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case 0xD2: // CMP DP Indirect
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// CMP();
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CMP(DirectPageIndirect());
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break;
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case 0xD3: // CMP SR Indirect Indexed, Y
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// CMP();
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CMP(StackRelativeIndirectIndexedY());
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break;
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case 0xD5: // CMP DP Indexed, X
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// CMP();
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CMP(DirectPageIndexedX());
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break;
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case 0xD7: // CMP DP Indirect Long Indexed, Y
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// CMP();
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CMP(DirectPageIndirectLongIndexedY());
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break;
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case 0xD9: // CMP Absolute Indexed, Y
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// CMP();
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CMP(AbsoluteIndexedY());
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break;
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case 0xDD: // CMP Absolute Indexed, X
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// CMP();
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CMP(AbsoluteIndexedX());
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break;
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case 0xDF: // CMP Absolute Long Indexed, X
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// CMP();
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CMP(AbsoluteLongIndexedX());
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break;
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case 0x02: // COP Coprocessor
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@@ -356,19 +372,19 @@ void CPU::ExecuteInstruction(uint8_t opcode) {
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break;
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case 0x3A: // DEC Accumulator
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// DEC();
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DEC(A);
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break;
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case 0xC6: // DEC Direct Page
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// DEC();
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DEC(DirectPage());
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break;
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case 0xCE: // DEC Absolute
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// DEC();
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DEC(Absolute());
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break;
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case 0xD6: // DEC DP Indexed, X
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// DEC();
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DEC(DirectPageIndexedX());
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break;
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case 0xDE: // DEC Absolute Indexed, X
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// DEC();
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DEC(AbsoluteIndexedX());
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break;
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case 0xCA: // DEX Decrement X register
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@@ -380,49 +396,49 @@ void CPU::ExecuteInstruction(uint8_t opcode) {
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break;
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case 0x41: // EOR DP Indexed Indirect, X
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// EOR();
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EOR(DirectPageIndexedIndirectX());
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break;
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case 0x43: // EOR Stack Relative
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// EOR();
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EOR(StackRelative());
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break;
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case 0x45: // EOR Direct Page
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// EOR();
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EOR(DirectPage());
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break;
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case 0x47: // EOR DP Indirect Long
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// EOR();
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EOR(DirectPageIndirectLong());
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break;
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case 0x49: // EOR Immediate
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// EOR();
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EOR(Immediate(), true);
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break;
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case 0x4D: // EOR Absolute
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// EOR();
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EOR(Absolute());
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break;
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case 0x4F: // EOR Absolute Long
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// EOR();
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EOR(AbsoluteLong());
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break;
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case 0x51: // EOR DP Indirect Indexed, Y
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// EOR();
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EOR(DirectPageIndirectIndexedY());
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break;
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case 0x52: // EOR DP Indirect
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// EOR();
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EOR(DirectPageIndirect());
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break;
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case 0x53: // EOR SR Indirect Indexed, Y
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// EOR();
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EOR(StackRelativeIndirectIndexedY());
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break;
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case 0x55: // EOR DP Indexed, X
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// EOR();
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EOR(DirectPageIndexedX());
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break;
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case 0x57: // EOR DP Indirect Long Indexed, Y
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// EOR();
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EOR(DirectPageIndirectLongIndexedY());
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break;
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case 0x59: // EOR Absolute Indexed, Y
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// EOR();
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EOR(AbsoluteIndexedY());
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break;
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case 0x5D: // EOR Absolute Indexed, X
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// EOR();
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EOR(AbsoluteIndexedX());
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break;
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case 0x5F: // EOR Absolute Long Indexed, X
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// EOR();
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EOR(AbsoluteLongIndexedX());
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break;
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case 0x1A: // INC Accumulator
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@@ -524,51 +540,51 @@ void CPU::ExecuteInstruction(uint8_t opcode) {
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break;
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case 0xA2: // LDX Immediate
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// LDX();
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LDX(Immediate(), true);
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break;
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case 0xA6: // LDX Direct Page
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// LDX();
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LDX(DirectPage());
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break;
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case 0xAE: // LDX Absolute
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// LDX();
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LDX(Absolute());
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break;
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case 0xB6: // LDX DP Indexed, Y
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// LDX();
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LDX(DirectPageIndexedY());
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break;
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case 0xBE: // LDX Absolute Indexed, Y
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// LDX();
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LDX(AbsoluteIndexedY());
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break;
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case 0xA0: // LDY Immediate
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// LDY();
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LDY(Immediate(), true);
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break;
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case 0xA4: // LDY Direct Page
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// LDY();
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LDY(DirectPage());
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break;
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case 0xAC: // LDY Absolute
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// LDY();
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LDY(Absolute());
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break;
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case 0xB4: // LDY DP Indexed, X
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// LDY();
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LDY(DirectPageIndexedX());
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break;
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case 0xBC: // LDY Absolute Indexed, X
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// LDY();
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LDY(AbsoluteIndexedX());
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break;
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case 0x46: // LSR Direct Page
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// LSR();
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LSR(DirectPage());
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break;
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case 0x4A: // LSR Accumulator
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// LSR();
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LSR(A);
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break;
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case 0x4E: // LSR Absolute
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// LSR();
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LSR(Absolute());
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break;
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case 0x56: // LSR DP Indexed, X
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// LSR();
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LSR(DirectPageIndexedX());
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break;
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case 0x5E: // LSR Absolute Indexed, X
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// LSR();
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LSR(AbsoluteIndexedX());
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break;
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case 0x54: // MVN Block Move Next
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@@ -580,61 +596,61 @@ void CPU::ExecuteInstruction(uint8_t opcode) {
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break;
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case 0x01: // ORA DP Indexed Indirect, X
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// ORA();
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ORA(DirectPageIndexedIndirectX());
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break;
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case 0x03: // ORA Stack Relative
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// ORA();
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ORA(StackRelative());
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break;
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case 0x05: // ORA Direct Page
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// ORA();
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ORA(DirectPage());
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break;
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case 0x07: // ORA DP Indirect Long
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// ORA();
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ORA(DirectPageIndirectLong());
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break;
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case 0x09: // ORA Immediate
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// ORA();
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ORA(Immediate(), true);
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break;
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case 0x0D: // ORA Absolute
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// ORA();
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ORA(Absolute());
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break;
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case 0x0F: // ORA Absolute Long
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// ORA();
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ORA(AbsoluteLong());
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break;
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case 0x11: // ORA DP Indirect Indexed, Y
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// ORA();
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ORA(DirectPageIndirectIndexedY());
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break;
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case 0x12: // ORA DP Indirect
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// ORA();
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ORA(DirectPageIndirect());
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break;
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case 0x13: // ORA SR Indirect Indexed, Y
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// ORA();
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ORA(StackRelativeIndirectIndexedY());
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break;
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case 0x15: // ORA DP Indexed, X
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// ORA();
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ORA(DirectPageIndexedX());
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break;
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case 0x17: // ORA DP Indirect Long Indexed, Y
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// ORA();
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ORA(DirectPageIndirectLongIndexedY());
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break;
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case 0x19: // ORA Absolute Indexed, Y
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// ORA();
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ORA(AbsoluteIndexedY());
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break;
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case 0x1D: // ORA Absolute Indexed, X
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// ORA();
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ORA(AbsoluteIndexedX());
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break;
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case 0x1F: // ORA Absolute Long Indexed, X
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// ORA();
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ORA(AbsoluteLongIndexedX());
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break;
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case 0xF4: // PEA Push Effective Absolute address
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// PEA();
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PEA();
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break;
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case 0xD4: // PEI Push Effective Indirect address
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// PEI();
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PEI();
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break;
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case 0x62: // PER Push Effective PC Relative Indirect address
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// PER();
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PER();
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break;
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case 0x48: // PHA Push Accumulator
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@@ -694,94 +710,93 @@ void CPU::ExecuteInstruction(uint8_t opcode) {
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break;
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case 0x26: // ROL Direct Page
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// ROL();
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ROL(DirectPage());
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break;
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case 0x2A: // ROL Accumulator
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// ROL();
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ROL(A);
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break;
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case 0x2E: // ROL Absolute
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// ROL();
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ROL(Absolute());
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break;
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case 0x36: // ROL DP Indexed, X
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// ROL();
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ROL(DirectPageIndexedX());
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break;
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case 0x3E: // ROL Absolute Indexed, X
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// ROL();
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ROL(AbsoluteIndexedX());
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break;
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case 0x66: // ROR Direct Page
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// ROR();
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ROR(DirectPage());
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break;
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case 0x6A: // ROR Accumulator
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// ROR();
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ROR(A);
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break;
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case 0x6E: // ROR Absolute
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// ROR();
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ROR(Absolute());
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break;
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case 0x76: // ROR DP Indexed, X
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// ROR();
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ROR(DirectPageIndexedX());
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break;
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case 0x7E: // ROR Absolute Indexed, X
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// ROR();
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ROR(AbsoluteIndexedX());
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break;
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case 0x40: // RTI Return from interrupt
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// RTI();
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RTI();
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break;
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case 0x6B: // RTL Return from subroutine long
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// RTL();
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RTL();
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break;
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case 0x60: // RTS Return from subroutine
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// RTS();
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RTS();
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break;
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case 0xE1: // SBC DP Indexed Indirect, X
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// SBC();
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SBC(DirectPageIndexedIndirectX());
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break;
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case 0xE3: // SBC Stack Relative
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// SBC();
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SBC(StackRelative());
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break;
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case 0xE5: // SBC Direct Page
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// SBC();
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SBC(DirectPage());
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break;
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case 0xE7: // SBC DP Indirect Long
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// SBC();
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SBC(DirectPageIndirectLong());
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break;
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case 0xE9: // SBC Immediate
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// SBC();
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SBC(Immediate(), true);
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break;
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case 0xED: // SBC Absolute
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// SBC();
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SBC(Absolute());
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break;
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case 0xEF: // SBC Absolute Long
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// SBC();
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SBC(AbsoluteLong());
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break;
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case 0xF1: // SBC DP Indirect Indexed, Y
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// SBC();
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SBC(DirectPageIndirectIndexedY());
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break;
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case 0xF2: // SBC DP Indirect
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// SBC();
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SBC(DirectPageIndirect());
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break;
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case 0xF3: // SBC SR Indirect Indexed, Y
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// SBC();
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SBC(StackRelativeIndirectIndexedY());
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break;
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case 0xF5: // SBC DP Indexed, X
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// SBC();
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SBC(DirectPageIndexedX());
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break;
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case 0xF7: // SBC DP Indirect Long Indexed, Y
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// SBC();
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SBC(DirectPageIndirectLongIndexedY());
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break;
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case 0xF9: // SBC Absolute Indexed, Y
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// SBC();
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SBC(AbsoluteIndexedY());
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break;
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case 0xFD: // SBC Absolute Indexed, X
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// SBC();
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SBC(AbsoluteIndexedX());
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break;
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case 0xFF: // SBC Absolute Long Indexed, X
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// SBC();
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SBC(AbsoluteLongIndexedX());
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break;
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case 0x38: // SEC Set carry
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@@ -801,90 +816,90 @@ void CPU::ExecuteInstruction(uint8_t opcode) {
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break;
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case 0x81: // STA DP Indexed Indirect, X
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// STA();
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STA(DirectPageIndexedIndirectX());
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break;
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case 0x83: // STA Stack Relative
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// STA();
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STA(StackRelative());
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break;
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case 0x85: // STA Direct Page
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// STA();
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STA(DirectPage());
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break;
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case 0x87: // STA DP Indirect Long
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// STA();
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STA(DirectPageIndirectLong());
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break;
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case 0x8D: // STA Absolute
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// STA();
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STA(Absolute());
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break;
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case 0x8F: // STA Absolute Long
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// STA();
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STA(AbsoluteLong());
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break;
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case 0x91: // STA DP Indirect Indexed, Y
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// STA();
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STA(DirectPageIndirectIndexedY());
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break;
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case 0x92: // STA DP Indirect
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// STA();
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STA(DirectPageIndirect());
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break;
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case 0x93: // STA SR Indirect Indexed, Y
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// STA();
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STA(StackRelativeIndirectIndexedY());
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break;
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case 0x95: // STA DP Indexed, X
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// STA();
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STA(DirectPageIndexedX());
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break;
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case 0x97: // STA DP Indirect Long Indexed, Y
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// STA();
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STA(DirectPageIndirectLongIndexedY());
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break;
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case 0x99: // STA Absolute Indexed, Y
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// STA();
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STA(AbsoluteIndexedY());
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break;
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case 0x9D: // STA Absolute Indexed, X
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// STA();
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STA(AbsoluteIndexedX());
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break;
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case 0x9F: // STA Absolute Long Indexed, X
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// STA();
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STA(AbsoluteLongIndexedX());
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break;
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case 0xDB: // STP Stop the clock
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// STP();
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STP();
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break;
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case 0x86: // STX Direct Page
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// STX();
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STX(DirectPage());
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break;
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case 0x8E: // STX Absolute
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// STX();
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STX(Absolute());
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break;
|
||||
case 0x96: // STX DP Indexed, Y
|
||||
// STX();
|
||||
STX(DirectPageIndexedY());
|
||||
break;
|
||||
|
||||
case 0x84: // STY Direct Page
|
||||
// STY();
|
||||
STY(DirectPage());
|
||||
break;
|
||||
case 0x8C: // STY Absolute
|
||||
// STY();
|
||||
STY(Absolute());
|
||||
break;
|
||||
case 0x94: // STY DP Indexed, X
|
||||
// STY();
|
||||
STY(DirectPageIndexedX());
|
||||
break;
|
||||
|
||||
case 0x64: // STZ Direct Page
|
||||
// STZ();
|
||||
STZ(DirectPage());
|
||||
break;
|
||||
case 0x74: // STZ DP Indexed, X
|
||||
// STZ();
|
||||
STZ(DirectPageIndexedX());
|
||||
break;
|
||||
case 0x9C: // STZ Absolute
|
||||
// STZ();
|
||||
STZ(Absolute());
|
||||
break;
|
||||
case 0x9E: // STZ Absolute Indexed, X
|
||||
// STZ();
|
||||
STZ(AbsoluteIndexedX());
|
||||
break;
|
||||
|
||||
case 0xAA: // TAX
|
||||
case 0xAA: // TAX Transfer accumulator to X
|
||||
TAX();
|
||||
break;
|
||||
|
||||
case 0xA8: // TAY
|
||||
case 0xA8: // TAY Transfer accumulator to Y
|
||||
TAY();
|
||||
break;
|
||||
|
||||
@@ -901,58 +916,56 @@ void CPU::ExecuteInstruction(uint8_t opcode) {
|
||||
break;
|
||||
|
||||
case 0x14: // TRB Direct Page
|
||||
// TRB();
|
||||
TRB(DirectPage());
|
||||
break;
|
||||
|
||||
case 0x1C: // TRB Absolute
|
||||
// TRB();
|
||||
TRB(Absolute());
|
||||
break;
|
||||
|
||||
case 0x04: // TSB Direct Page
|
||||
// TSB();
|
||||
TSB(DirectPage());
|
||||
break;
|
||||
|
||||
case 0x0C: // TSB Absolute
|
||||
// TSB();
|
||||
TSB(Absolute());
|
||||
break;
|
||||
|
||||
case 0x3B: // TSC
|
||||
TSC();
|
||||
break;
|
||||
|
||||
case 0xBA: // TSX
|
||||
case 0xBA: // TSX Transfer stack pointer to X
|
||||
TSX();
|
||||
break;
|
||||
|
||||
case 0x8A: // TXA
|
||||
case 0x8A: // TXA Transfer X to accumulator
|
||||
TXA();
|
||||
break;
|
||||
|
||||
case 0x9A: // TXS
|
||||
case 0x9A: // TXS Transfer X to stack pointer
|
||||
TXS();
|
||||
break;
|
||||
|
||||
case 0x9B: // TXY
|
||||
case 0x9B: // TXY Transfer X to Y
|
||||
TXY();
|
||||
break;
|
||||
|
||||
case 0x98: // TYA
|
||||
case 0x98: // TYA Transfer Y to accumulator
|
||||
TYA();
|
||||
break;
|
||||
|
||||
case 0xBB: // TYX
|
||||
case 0xBB: // TYX Transfer Y to X
|
||||
TYX();
|
||||
break;
|
||||
|
||||
case 0xCB: // WAI
|
||||
// WAI();
|
||||
case 0xCB: // WAI Wait for interrupt
|
||||
WAI();
|
||||
break;
|
||||
|
||||
case 0xEB: // XBA
|
||||
// XBA();
|
||||
case 0xEB: // XBA Exchange B and A
|
||||
XBA();
|
||||
break;
|
||||
|
||||
case 0xFB: // XCE
|
||||
case 0xFB: // XCE Exchange carry and emulation bits
|
||||
XCE();
|
||||
break;
|
||||
default:
|
||||
@@ -961,29 +974,26 @@ void CPU::ExecuteInstruction(uint8_t opcode) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void CPU::ADC(uint8_t operand) {
|
||||
auto C = GetCarryFlag();
|
||||
if (!E) { // 8-bit mode
|
||||
uint16_t result = (A & 0xFF) + (operand & 0xFF); // + (C ? 1 : 0);
|
||||
SetCarryFlag(!(result > 0xFF)); // Update the carry flag
|
||||
bool C = GetCarryFlag();
|
||||
if (GetAccumulatorSize()) { // 8-bit mode
|
||||
uint16_t result = static_cast<uint16_t>(A & 0xFF) +
|
||||
static_cast<uint16_t>(operand) + (C ? 1 : 0);
|
||||
SetCarryFlag(result > 0xFF); // Update the carry flag
|
||||
|
||||
// Update the overflow flag
|
||||
bool overflow = (~(A ^ operand) & (A ^ result) & 0x80) != 0;
|
||||
if (overflow) {
|
||||
status |= 0x40; // Set overflow flag
|
||||
} else {
|
||||
status &= ~0x40; // Clear overflow flag
|
||||
}
|
||||
SetOverflowFlag(overflow);
|
||||
|
||||
// Update the accumulator
|
||||
// Update the accumulator with proper wrap-around
|
||||
A = (A & 0xFF00) | (result & 0xFF);
|
||||
|
||||
SetZeroFlag(A == 0);
|
||||
SetZeroFlag((A & 0xFF) == 0);
|
||||
SetNegativeFlag(A & 0x80);
|
||||
} else {
|
||||
uint32_t result = A + operand; // + (C ? 1 : 0);
|
||||
SetCarryFlag(!(result > 0xFFFF)); // Update the carry flag
|
||||
uint32_t result =
|
||||
static_cast<uint32_t>(A) + static_cast<uint32_t>(operand) + (C ? 1 : 0);
|
||||
SetCarryFlag(result > 0xFFFF); // Update the carry flag
|
||||
|
||||
// Update the overflow flag
|
||||
bool overflow = (~(A ^ operand) & (A ^ result) & 0x8000) != 0;
|
||||
@@ -997,6 +1007,8 @@ void CPU::ADC(uint8_t operand) {
|
||||
}
|
||||
}
|
||||
|
||||
void CPU::HandleInterrupts() {}
|
||||
|
||||
void CPU::AND(uint16_t value, bool isImmediate) {
|
||||
uint16_t operand;
|
||||
if (E == 0) { // 16-bit mode
|
||||
|
||||
@@ -51,7 +51,9 @@ class CPU : public Memory, public Clock {
|
||||
|
||||
uint8_t FetchByteDirectPage(uint8_t operand);
|
||||
|
||||
void Run();
|
||||
void ExecuteInstruction(uint8_t opcode);
|
||||
void HandleInterrupts();
|
||||
|
||||
// ==========================================================================
|
||||
// Addressing Modes
|
||||
@@ -274,12 +276,11 @@ class CPU : public Memory, public Clock {
|
||||
// ==========================================================================
|
||||
// Registers
|
||||
|
||||
uint8_t A = 0; // Accumulator
|
||||
uint8_t B = 0; // Accumulator (High)
|
||||
uint16_t A = 0; // Accumulator
|
||||
uint16_t X = 0; // X index register
|
||||
uint16_t Y = 0; // Y index register
|
||||
uint16_t D = 0; // Direct Page register
|
||||
uint16_t DB = 0; // Data Bank register
|
||||
uint8_t DB = 0; // Data Bank register
|
||||
uint8_t PB = 0; // Program Bank register
|
||||
uint16_t PC = 0; // Program Counter
|
||||
uint8_t E = 1; // Emulation mode flag
|
||||
@@ -435,29 +436,76 @@ class CPU : public Memory, public Clock {
|
||||
// CLV: Clear overflow flag
|
||||
void CLV() { status &= ~0x40; }
|
||||
|
||||
// CMP: Compare ```
|
||||
// COP: Coprocessor ```
|
||||
// CMP: Compare TESTME
|
||||
// n Set if MSB of result is set; else cleared
|
||||
// z Set if result is zero; else cleared
|
||||
// c Set if no borrow; else cleared
|
||||
void CMP(uint8_t value, bool isImmediate = false) {
|
||||
if (GetAccumulatorSize()) { // 8-bit
|
||||
uint8_t result = isImmediate ? A - value : A - memory.ReadByte(value);
|
||||
SetZeroFlag(result == 0);
|
||||
SetNegativeFlag(result & 0x80);
|
||||
SetCarryFlag(A >= value);
|
||||
} else { // 16-bit
|
||||
uint16_t result = isImmediate ? A - value : A - memory.ReadWord(value);
|
||||
SetZeroFlag(result == 0);
|
||||
SetNegativeFlag(result & 0x8000);
|
||||
SetCarryFlag(A >= value);
|
||||
}
|
||||
}
|
||||
|
||||
// COP: Coprocessor TESTME
|
||||
void COP() {
|
||||
PC += 2; // Increment the program counter by 2
|
||||
memory.PushWord(PC);
|
||||
memory.PushByte(status);
|
||||
SetInterruptFlag(true);
|
||||
if (E) {
|
||||
PC = memory.ReadWord(0xFFF4);
|
||||
} else {
|
||||
PC = memory.ReadWord(0xFFE4);
|
||||
}
|
||||
SetDecimalFlag(false);
|
||||
}
|
||||
|
||||
// CPX: Compare X register
|
||||
// CPX: Compare X register
|
||||
void CPX(uint16_t value, bool isImmediate = false) {
|
||||
uint16_t memory_value = isImmediate
|
||||
? value
|
||||
: (GetIndexSize() ? memory.ReadByte(value)
|
||||
: memory.ReadWord(value));
|
||||
compare(X, memory_value);
|
||||
if (GetIndexSize()) { // 8-bit
|
||||
uint8_t memory_value = isImmediate ? value : memory.ReadByte(value);
|
||||
compare(X, memory_value);
|
||||
} else { // 16-bit
|
||||
uint16_t memory_value = isImmediate ? value : memory.ReadWord(value);
|
||||
compare(X, memory_value);
|
||||
}
|
||||
}
|
||||
|
||||
// CPY: Compare Y register
|
||||
void CPY(uint16_t value, bool isImmediate = false) {
|
||||
uint16_t memory_value = isImmediate
|
||||
? value
|
||||
: (GetIndexSize() ? memory.ReadByte(value)
|
||||
: memory.ReadWord(value));
|
||||
compare(Y, memory_value);
|
||||
if (GetIndexSize()) { // 8-bit
|
||||
uint8_t memory_value = isImmediate ? value : memory.ReadByte(value);
|
||||
compare(Y, memory_value);
|
||||
} else { // 16-bit
|
||||
uint16_t memory_value = isImmediate ? value : memory.ReadWord(value);
|
||||
compare(Y, memory_value);
|
||||
}
|
||||
}
|
||||
|
||||
// DEC: Decrement ```
|
||||
// DEC: Decrement TESTME
|
||||
void DEC(uint16_t address) {
|
||||
if (GetAccumulatorSize()) {
|
||||
uint8_t value = memory.ReadByte(address);
|
||||
value--;
|
||||
memory.WriteByte(address, value);
|
||||
SetZeroFlag(value == 0);
|
||||
SetNegativeFlag(value & 0x80);
|
||||
} else {
|
||||
uint16_t value = memory.ReadWord(address);
|
||||
value--;
|
||||
memory.WriteWord(address, value);
|
||||
SetZeroFlag(value == 0);
|
||||
SetNegativeFlag(value & 0x8000);
|
||||
}
|
||||
}
|
||||
|
||||
// DEX: Decrement X register
|
||||
void DEX() {
|
||||
@@ -485,7 +533,18 @@ class CPU : public Memory, public Clock {
|
||||
}
|
||||
}
|
||||
|
||||
// EOR: Exclusive OR ```
|
||||
// EOR: Exclusive OR TESTMEs
|
||||
void EOR(uint16_t address, bool isImmediate = false) {
|
||||
if (GetAccumulatorSize()) {
|
||||
A ^= isImmediate ? address : memory.ReadByte(address);
|
||||
SetZeroFlag(A == 0);
|
||||
SetNegativeFlag(A & 0x80);
|
||||
} else {
|
||||
A ^= isImmediate ? address : memory.ReadWord(address);
|
||||
SetZeroFlag(A == 0);
|
||||
SetNegativeFlag(A & 0x8000);
|
||||
}
|
||||
}
|
||||
|
||||
// INC: Increment
|
||||
void INC(uint16_t address) {
|
||||
@@ -779,7 +838,12 @@ class CPU : public Memory, public Clock {
|
||||
}
|
||||
}
|
||||
|
||||
// STP: Stop the clock ```
|
||||
// TODO: Make this work with the Clock class of the CPU
|
||||
// STP: Stop the clock
|
||||
void STP() {
|
||||
// During the next phase 2 clock cycle, stop the processors oscillator input
|
||||
// The processor is effectively shut down until a reset occurs (RES` pin).
|
||||
}
|
||||
|
||||
// STX: Store X register
|
||||
void STX(uint16_t address) {
|
||||
@@ -900,15 +964,20 @@ class CPU : public Memory, public Clock {
|
||||
SetNegativeFlag(Y & 0x80);
|
||||
}
|
||||
|
||||
// WAI: Wait for interrupt ```
|
||||
// TODO: Make this communicate with the SNES class
|
||||
// WAI: Wait for interrupt TESTME
|
||||
void WAI() {
|
||||
// Pull the RDY pin low
|
||||
// Power consumption is reduced(?)
|
||||
// RDY remains low until an external hardware interupt
|
||||
// (NMI, IRQ, ABORT, or RESET) is received from the SNES class
|
||||
}
|
||||
|
||||
// XBA: Exchange B and A accumulator
|
||||
void XBA() {
|
||||
uint8_t temp = A;
|
||||
A = B;
|
||||
B = temp;
|
||||
SetZeroFlag(A == 0);
|
||||
SetNegativeFlag(A & 0x80);
|
||||
uint8_t lowByte = A & 0xFF;
|
||||
uint8_t highByte = (A >> 8) & 0xFF;
|
||||
A = (lowByte << 8) | highByte;
|
||||
}
|
||||
|
||||
// XCE: Exchange Carry and Emulation Flags
|
||||
|
||||
@@ -5,6 +5,43 @@
|
||||
#include <iostream>
|
||||
#include <vector>
|
||||
|
||||
// LoROM (Mode 20):
|
||||
|
||||
// Banks Offset Purpose
|
||||
// 00-3F 0000-1FFF LowRAM (shadowed from 7E)
|
||||
// 2000-2FFF PPU1, APU
|
||||
// 3000-3FFF SFX, DSP, etc.
|
||||
// 4000-41FF Controller
|
||||
// 4200-5FFF PPU2, DMA, etc.
|
||||
// 6000-7FFF Expansion RAM (reserved)
|
||||
// 8000-FFFF 32k ROM Chunk
|
||||
// 40-7C 0000-7FFF 32k ROM Chunk
|
||||
// 8000-FFFF 32k ROM Chunk
|
||||
// 7D 0000-FFFF SRAM
|
||||
// 7E 0000-1FFF LowRAM
|
||||
// 2000-FFFF System RAM
|
||||
// 7F 0000-FFFF System RAM
|
||||
|
||||
// HiROM (Mode 21):
|
||||
|
||||
// Banks Offset Purpose
|
||||
// 00-3F 0000-1FFF LowRAM (shadowed from 7E)
|
||||
// 2000-2FFF PPU1, APU
|
||||
// 3000-3FFF SFX, DSP, etc.
|
||||
// 4000-41FF Controller
|
||||
// 4200-5FFF PPU2, DMA, etc.
|
||||
// 6000-7FFF SRAM (256KB)
|
||||
// 8000-FFFF 32k ROM Chunk
|
||||
// 40-6F 0000-FFFF 64k ROM Chunk
|
||||
// 70-77 0000-FFFF SRAM (256KB)
|
||||
// 78-7D 0000-FFFF Never Used
|
||||
// 7E 0000-1FFF LowRAM
|
||||
// 2000-7FFF HighRAM
|
||||
// 8000-FFFF Expanded RAM
|
||||
// 7F 0000-FFFF More Expanded RAM
|
||||
// 80-EF 0000-FFFF Mirror of 00-6F
|
||||
// F0-FF 0000-FFFF 64k ROM Chunk
|
||||
|
||||
namespace yaze {
|
||||
namespace app {
|
||||
namespace emu {
|
||||
@@ -103,6 +140,86 @@ class Memory {
|
||||
|
||||
class MemoryImpl : public Memory {
|
||||
public:
|
||||
void Initialize(const std::vector<uint8_t>& romData) {
|
||||
const size_t ROM_CHUNK_SIZE = 0x8000; // 32 KB
|
||||
const size_t SRAM_SIZE = 0x10000; // 64 KB
|
||||
const size_t SYSTEM_RAM_SIZE = 0x20000; // 128 KB
|
||||
const size_t EXPANSION_RAM_SIZE = 0x2000; // 8 KB
|
||||
const size_t HARDWARE_REGISTERS_SIZE = 0x4000; // 16 KB
|
||||
|
||||
// Clear memory
|
||||
memory_.clear();
|
||||
memory_.resize(0x1000000, 0); // 24-bit address space
|
||||
|
||||
// Load ROM data into memory based on LoROM mapping
|
||||
size_t romSize = romData.size();
|
||||
size_t romAddress = 0;
|
||||
for (size_t bank = 0x00; bank <= 0xBF; bank += 0x80) {
|
||||
for (size_t offset = 0x8000; offset <= 0xFFFF; offset += ROM_CHUNK_SIZE) {
|
||||
if (romAddress < romSize) {
|
||||
std::copy(romData.begin() + romAddress,
|
||||
romData.begin() + romAddress + ROM_CHUNK_SIZE,
|
||||
memory_.begin() + (bank << 16) + offset);
|
||||
romAddress += ROM_CHUNK_SIZE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Initialize SRAM at banks 0x7D and 0xFD
|
||||
std::fill(memory_.begin() + (0x7D << 16), memory_.begin() + (0x7E << 16),
|
||||
0);
|
||||
std::fill(memory_.begin() + (0xFD << 16), memory_.begin() + (0xFE << 16),
|
||||
0);
|
||||
|
||||
// Initialize System RAM at banks 0x7E and 0x7F
|
||||
std::fill(memory_.begin() + (0x7E << 16),
|
||||
memory_.begin() + (0x7E << 16) + SYSTEM_RAM_SIZE, 0);
|
||||
|
||||
// Initialize Shadow RAM at banks 0x00-0x3F and 0x80-0xBF
|
||||
for (size_t bank = 0x00; bank <= 0xBF; bank += 0x80) {
|
||||
std::fill(memory_.begin() + (bank << 16),
|
||||
memory_.begin() + (bank << 16) + 0x2000, 0);
|
||||
}
|
||||
|
||||
// Initialize Hardware Registers at banks 0x00-0x3F and 0x80-0xBF
|
||||
for (size_t bank = 0x00; bank <= 0xBF; bank += 0x80) {
|
||||
std::fill(
|
||||
memory_.begin() + (bank << 16) + 0x2000,
|
||||
memory_.begin() + (bank << 16) + 0x2000 + HARDWARE_REGISTERS_SIZE, 0);
|
||||
}
|
||||
|
||||
// Initialize Expansion RAM at banks 0x00-0x3F and 0x80-0xBF
|
||||
for (size_t bank = 0x00; bank <= 0xBF; bank += 0x80) {
|
||||
std::fill(memory_.begin() + (bank << 16) + 0x6000,
|
||||
memory_.begin() + (bank << 16) + 0x6000 + EXPANSION_RAM_SIZE,
|
||||
0);
|
||||
}
|
||||
|
||||
// Initialize Reset and NMI Vectors at bank 0xFF
|
||||
std::fill(memory_.begin() + (0xFF << 16) + 0xFF00,
|
||||
memory_.begin() + (0xFF << 16) + 0xFFFF + 1, 0);
|
||||
|
||||
// Copy data into rom_ vector
|
||||
rom_.resize(kROMSize);
|
||||
std::copy(memory_.begin() + kROMStart,
|
||||
memory_.begin() + kROMStart + kROMSize, rom_.begin());
|
||||
|
||||
// Copy data into ram_ vector
|
||||
ram_.resize(kRAMSize);
|
||||
std::copy(memory_.begin() + kRAMStart,
|
||||
memory_.begin() + kRAMStart + kRAMSize, ram_.begin());
|
||||
|
||||
// Copy data into vram_ vector
|
||||
vram_.resize(kVRAMSize);
|
||||
std::copy(memory_.begin() + kVRAMStart,
|
||||
memory_.begin() + kVRAMStart + kVRAMSize, vram_.begin());
|
||||
|
||||
// Copy data into oam_ vector
|
||||
oam_.resize(kOAMSize);
|
||||
std::copy(memory_.begin() + kOAMStart,
|
||||
memory_.begin() + kOAMStart + kOAMSize, oam_.begin());
|
||||
}
|
||||
|
||||
uint8_t ReadByte(uint16_t address) const override {
|
||||
uint32_t mapped_address = GetMappedAddress(address);
|
||||
return memory_.at(mapped_address);
|
||||
@@ -174,6 +291,7 @@ class MemoryImpl : public Memory {
|
||||
(static_cast<uint32_t>(mid) << 8) | low;
|
||||
}
|
||||
|
||||
// Stack Pointer access.
|
||||
int16_t SP() const override { return SP_; }
|
||||
void SetSP(int16_t value) override { SP_ = value; }
|
||||
|
||||
|
||||
@@ -14,6 +14,30 @@ namespace yaze {
|
||||
namespace app {
|
||||
namespace emu {
|
||||
|
||||
namespace {
|
||||
uint8_t GetHeaderOffset(const Memory& memory) {
|
||||
uint8_t mapMode = memory[(0x00 << 16) + 0xFFD5];
|
||||
uint8_t offset;
|
||||
|
||||
switch (mapMode & 0x07) {
|
||||
case 0: // LoROM
|
||||
offset = 0x7F;
|
||||
break;
|
||||
case 1: // HiROM
|
||||
offset = 0xFF;
|
||||
break;
|
||||
case 5: // ExHiROM
|
||||
offset = 0x40;
|
||||
break;
|
||||
default:
|
||||
throw std::runtime_error("Unsupported map mode");
|
||||
}
|
||||
|
||||
return offset;
|
||||
}
|
||||
|
||||
} // namespace
|
||||
|
||||
void DMA::StartDMATransfer(uint8_t channelMask) {
|
||||
for (int i = 0; i < 8; ++i) {
|
||||
if ((channelMask & (1 << i)) != 0) {
|
||||
@@ -78,7 +102,63 @@ void DMA::EnableHDMATransfers(uint8_t channelMask) {
|
||||
HDMAEN = channelMask; // Set the HDMAEN register to the channel mask
|
||||
}
|
||||
|
||||
ROMInfo SNES::ReadRomHeader(uint32_t offset) {
|
||||
ROMInfo romInfo;
|
||||
|
||||
// Read cartridge title
|
||||
char title[22];
|
||||
for (int i = 0; i < 21; ++i) {
|
||||
title[i] = cpu.ReadByte(offset + i);
|
||||
}
|
||||
title[21] = '\0'; // Null-terminate the string
|
||||
romInfo.title = std::string(title);
|
||||
|
||||
// Read ROM speed and memory map mode
|
||||
uint8_t romSpeedAndMapMode = cpu.ReadByte(offset + 0x15);
|
||||
romInfo.romSpeed = (ROMSpeed)(romSpeedAndMapMode & 0x07);
|
||||
romInfo.bankSize = (BankSize)((romSpeedAndMapMode >> 5) & 0x01);
|
||||
|
||||
// Read ROM type
|
||||
romInfo.romType = (ROMType)cpu.ReadByte(offset + 0x16);
|
||||
|
||||
// Read ROM size
|
||||
romInfo.romSize = (ROMSize)cpu.ReadByte(offset + 0x17);
|
||||
|
||||
// Read RAM size
|
||||
romInfo.sramSize = (SRAMSize)cpu.ReadByte(offset + 0x18);
|
||||
|
||||
// Read country code
|
||||
romInfo.countryCode = (CountryCode)cpu.ReadByte(offset + 0x19);
|
||||
|
||||
// Read license
|
||||
romInfo.license = (License)cpu.ReadByte(offset + 0x1A);
|
||||
|
||||
// Read ROM version
|
||||
romInfo.version = cpu.ReadByte(offset + 0x1B);
|
||||
|
||||
// Read checksum complement
|
||||
romInfo.checksumComplement = cpu.ReadWord(offset + 0x1E);
|
||||
|
||||
// Read checksum
|
||||
romInfo.checksum = cpu.ReadWord(offset + 0x1C);
|
||||
|
||||
// Read NMI VBL vector
|
||||
romInfo.nmiVblVector = cpu.ReadWord(offset + 0x3E);
|
||||
|
||||
// Read reset vector
|
||||
romInfo.resetVector = cpu.ReadWord(offset + 0x3C);
|
||||
|
||||
return romInfo;
|
||||
}
|
||||
|
||||
void SNES::Init(ROM& rom) {
|
||||
// Load the ROM into memory and set up the memory mapping
|
||||
memory_.Initialize(rom.vector());
|
||||
|
||||
// Read the ROM header
|
||||
auto header_offset = GetHeaderOffset(memory_);
|
||||
rom_info_ = ReadRomHeader(header_offset);
|
||||
|
||||
// Perform a long jump into a FastROM bank (if the ROM speed is FastROM)
|
||||
// Disable the emulation flag (switch to 65816 native mode)s
|
||||
cpu.Init();
|
||||
@@ -237,7 +317,7 @@ void SNES::Run() {
|
||||
|
||||
// Enable NMI Interrupts
|
||||
void SNES::EnableVBlankInterrupts() {
|
||||
vBlankFlag = 0;
|
||||
vBlankFlag = false;
|
||||
|
||||
// Clear the RDNMI VBlank flag
|
||||
memory_.ReadByte(0x4210); // RDNMI
|
||||
@@ -248,7 +328,7 @@ void SNES::EnableVBlankInterrupts() {
|
||||
|
||||
// Wait until the VBlank routine has been processed
|
||||
void SNES::WaitForVBlank() {
|
||||
vBlankFlag = 1;
|
||||
vBlankFlag = true;
|
||||
|
||||
// Loop until `vBlankFlag` is clear
|
||||
while (vBlankFlag) {
|
||||
|
||||
@@ -62,6 +62,8 @@ class SNES : public DMA {
|
||||
SNES() = default;
|
||||
~SNES() = default;
|
||||
|
||||
ROMInfo ReadRomHeader(uint32_t offset);
|
||||
|
||||
// Initialization
|
||||
void Init(ROM& rom);
|
||||
|
||||
@@ -110,6 +112,7 @@ class SNES : public DMA {
|
||||
APU apu{memory_};
|
||||
|
||||
// Helper classes
|
||||
ROMInfo rom_info_;
|
||||
Debugger debugger;
|
||||
|
||||
std::vector<uint8_t> rom_data;
|
||||
|
||||
Reference in New Issue
Block a user