backend-infra-engineer: Pre-0.2.2 2024 Q3 snapshot
This commit is contained in:
scawful
@@ -1,6 +1,6 @@
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#include "app/emu/memory/memory.h"
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#include <imgui/imgui.h>
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#include "imgui/imgui.h"
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#include <cstdint>
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#include <iostream>
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@@ -14,6 +14,210 @@ namespace app {
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namespace emu {
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namespace memory {
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void MemoryImpl::Initialize(const std::vector<uint8_t>& romData, bool verbose) {
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verbose_ = verbose;
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type_ = 1;
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auto location = 0x7FC0; // GetHeaderOffset();
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romSize = 0x400 << romData[location + 0x17];
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sramSize = 0x400 << romData[location + 0x18];
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rom_.resize(romSize);
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// Copy memory into rom_
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for (size_t i = 0; i < romSize; i++) {
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rom_[i] = romData[i];
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}
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ram_.resize(sramSize);
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for (size_t i = 0; i < sramSize; i++) {
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ram_[i] = 0;
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}
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// Clear memory
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memory_.resize(0x1000000); // 16 MB
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std::fill(memory_.begin(), memory_.end(), 0);
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// Load ROM data into memory based on LoROM mapping
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size_t romSize = romData.size();
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size_t romAddress = 0;
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const size_t ROM_CHUNK_SIZE = 0x8000; // 32 KB
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for (size_t bank = 0x00; bank <= 0x3F; ++bank) {
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for (size_t offset = 0x8000; offset <= 0xFFFF; offset += ROM_CHUNK_SIZE) {
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if (romAddress < romSize) {
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std::copy(romData.begin() + romAddress,
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romData.begin() + romAddress + ROM_CHUNK_SIZE,
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memory_.begin() + (bank << 16) + offset);
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romAddress += ROM_CHUNK_SIZE;
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}
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}
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}
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}
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memory::RomInfo MemoryImpl::ReadRomHeader() {
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memory::RomInfo romInfo;
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uint32_t offset = GetHeaderOffset();
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// Read cartridge title
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char title[22];
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for (int i = 0; i < 21; ++i) {
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title[i] = ReadByte(offset + i);
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}
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title[21] = '\0'; // Null-terminate the string
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romInfo.title = std::string(title);
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// Read ROM speed and memory map mode
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uint8_t romSpeedAndMapMode = ReadByte(offset + 0x15);
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romInfo.romSpeed = (memory::RomSpeed)(romSpeedAndMapMode & 0x07);
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romInfo.bankSize = (memory::BankSize)((romSpeedAndMapMode >> 5) & 0x01);
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// Read ROM type
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romInfo.romType = (memory::RomType)ReadByte(offset + 0x16);
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// Read ROM size
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romInfo.romSize = (memory::RomSize)ReadByte(offset + 0x17);
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// Read RAM size
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romInfo.sramSize = (memory::SramSize)ReadByte(offset + 0x18);
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// Read country code
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romInfo.countryCode = (memory::CountryCode)ReadByte(offset + 0x19);
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// Read license
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romInfo.license = (memory::License)ReadByte(offset + 0x1A);
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// Read ROM version
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romInfo.version = ReadByte(offset + 0x1B);
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// Read checksum complement
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romInfo.checksumComplement = ReadWord(offset + 0x1E);
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// Read checksum
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romInfo.checksum = ReadWord(offset + 0x1C);
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// Read NMI VBL vector
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romInfo.nmiVblVector = ReadWord(offset + 0x3E);
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// Read reset vector
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romInfo.resetVector = ReadWord(offset + 0x3C);
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return romInfo;
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}
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uint8_t MemoryImpl::cart_read(uint8_t bank, uint16_t adr) {
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switch (type_) {
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case 0:
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return open_bus_;
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case 1:
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return cart_readLorom(bank, adr);
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case 2:
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return cart_readHirom(bank, adr);
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case 3:
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return cart_readExHirom(bank, adr);
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}
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return open_bus_;
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}
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void MemoryImpl::cart_write(uint8_t bank, uint16_t adr, uint8_t val) {
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switch (type_) {
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case 0:
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break;
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case 1:
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cart_writeLorom(bank, adr, val);
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break;
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case 2:
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cart_writeHirom(bank, adr, val);
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break;
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case 3:
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cart_writeHirom(bank, adr, val);
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break;
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}
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}
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uint8_t MemoryImpl::cart_readLorom(uint8_t bank, uint16_t adr) {
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if (((bank >= 0x70 && bank < 0x7e) || bank >= 0xf0) && adr < 0x8000 &&
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sramSize > 0) {
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// banks 70-7e and f0-ff, adr 0000-7fff
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return ram_[(((bank & 0xf) << 15) | adr) & (sramSize - 1)];
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}
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bank &= 0x7f;
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if (adr >= 0x8000 || bank >= 0x40) {
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// adr 8000-ffff in all banks or all addresses in banks 40-7f and c0-ff
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return rom_[((bank << 15) | (adr & 0x7fff)) & (romSize - 1)];
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}
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return open_bus_;
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}
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void MemoryImpl::cart_writeLorom(uint8_t bank, uint16_t adr, uint8_t val) {
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if (((bank >= 0x70 && bank < 0x7e) || bank > 0xf0) && adr < 0x8000 &&
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sramSize > 0) {
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// banks 70-7e and f0-ff, adr 0000-7fff
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ram_[(((bank & 0xf) << 15) | adr) & (sramSize - 1)] = val;
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}
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}
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uint8_t MemoryImpl::cart_readHirom(uint8_t bank, uint16_t adr) {
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bank &= 0x7f;
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if (bank < 0x40 && adr >= 0x6000 && adr < 0x8000 && sramSize > 0) {
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// banks 00-3f and 80-bf, adr 6000-7fff
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return ram_[(((bank & 0x3f) << 13) | (adr & 0x1fff)) & (sramSize - 1)];
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}
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if (adr >= 0x8000 || bank >= 0x40) {
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// adr 8000-ffff in all banks or all addresses in banks 40-7f and c0-ff
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return rom_[(((bank & 0x3f) << 16) | adr) & (romSize - 1)];
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}
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return open_bus_;
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}
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uint8_t MemoryImpl::cart_readExHirom(uint8_t bank, uint16_t adr) {
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if ((bank & 0x7f) < 0x40 && adr >= 0x6000 && adr < 0x8000 && sramSize > 0) {
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// banks 00-3f and 80-bf, adr 6000-7fff
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return ram_[(((bank & 0x3f) << 13) | (adr & 0x1fff)) & (sramSize - 1)];
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}
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bool secondHalf = bank < 0x80;
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bank &= 0x7f;
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if (adr >= 0x8000 || bank >= 0x40) {
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// adr 8000-ffff in all banks or all addresses in banks 40-7f and c0-ff
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return rom_[(((bank & 0x3f) << 16) | (secondHalf ? 0x400000 : 0) | adr) &
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(romSize - 1)];
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}
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return open_bus_;
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}
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void MemoryImpl::cart_writeHirom(uint8_t bank, uint16_t adr, uint8_t val) {
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bank &= 0x7f;
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if (bank < 0x40 && adr >= 0x6000 && adr < 0x8000 && sramSize > 0) {
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// banks 00-3f and 80-bf, adr 6000-7fff
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ram_[(((bank & 0x3f) << 13) | (adr & 0x1fff)) & (sramSize - 1)] = val;
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}
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}
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uint32_t MemoryImpl::GetMappedAddress(uint32_t address) const {
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uint8_t bank = address >> 16;
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uint32_t offset = address & 0xFFFF;
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if (bank <= 0x3F) {
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if (address <= 0x1FFF) {
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return (0x7E << 16) + offset; // Shadow RAM
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} else if (address <= 0x5FFF) {
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return (bank << 16) + (offset - 0x2000) + 0x2000; // Hardware Registers
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} else if (address <= 0x7FFF) {
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return offset - 0x6000 + 0x6000; // Expansion RAM
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} else {
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// Return lorom mapping
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return (bank << 16) + (offset - 0x8000) + 0x8000; // ROM
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}
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} else if (bank == 0x7D) {
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return offset + 0x7D0000; // SRAM
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} else if (bank == 0x7E || bank == 0x7F) {
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return offset + 0x7E0000; // System RAM
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} else if (bank >= 0x80) {
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// Handle HiROM and mirrored areas
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}
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return address; // Return the original address if no mapping is defined
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}
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void DrawSnesMemoryMapping(const MemoryImpl& memory) {
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// Using those as a base value to create width/height that are factor of the
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// size of our font
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