Add StackPointer to memory, PHA, PLA, PHP, PLP
This commit is contained in:
scawful
@@ -11,101 +11,21 @@ namespace yaze {
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namespace app {
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namespace emu {
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// ADC: Add with carry
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// AND: Logical AND
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// ASL: Arithmetic shift left
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// BCC: Branch if carry clear
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// BCS: Branch if carry set
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// BEQ: Branch if equal (zero set)
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// BIT: Bit test
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// BMI: Branch if minus (negative set)
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// BNE: Branch if not equal (zero clear)
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// BPL: Branch if plus (negative clear)
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// BRA: Branch always
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// BRK: Break
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// BRL: Branch always long
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// BVC: Branch if overflow clear
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// BVS: Branch if overflow set
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// CLC: Clear carry
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// CLD: Clear decimal
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// CLI: Clear interrupt disable
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// CLV: Clear overflow
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// CMP: Compare
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// COP: Coprocessor
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// CPX: Compare X register
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// CPY: Compare Y register
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// DEC: Decrement
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// DEX: Decrement X register
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// DEY: Decrement Y register
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// EOR: Exclusive OR
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// INC: Increment
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// INX: Increment X register
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// INY: Increment Y register
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// JMP: Jump
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// JML: Jump long
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// JSR: Jump to subroutine
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// JSL: Jump to subroutine long
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// LDA: Load accumulator
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// LDX: Load X register
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// LDY: Load Y register
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// LSR: Logical shift right
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// MVN: Move negative
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// MVP: Move positive
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// NOP: No operation
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// ORA: Logical OR
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// PEA: Push effective address
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// PEI: Push effective indirect address
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// PER: Push effective PC-relative address
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// PHA: Push accumulator
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// PHB: Push data bank register
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// PHD: Push direct page register
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// PHK: Push program bank register
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// PHP: Push processor status register
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// PHX: Push X register
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// PHY: Push Y register
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// PLA: Pull accumulator
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// PLB: Pull data bank register
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// PLD: Pull direct page register
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// PLP: Pull processor status register
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// PLX: Pull X register
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// PLY: Pull Y register
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// ROL: Rotate left
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// ROR: Rotate right
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// RTI: Return from interrupt
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// RTL: Return from subroutine long
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// RTS: Return from subroutine
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// SBC: Subtract with carry
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// STA: Store accumulator
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// STP: Stop the clock
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// STX: Store X register
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// STY: Store Y register
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// STZ: Store zero
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// TDC: Transfer direct page register to accumulator
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// TRB: Test and reset bits
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// TSB: Test and set bits
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// WAI: Wait for interrupt
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// XBA: Exchange B and A accumulator
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// XCE: Exchange carry and emulation
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class CPU : public Memory {
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private:
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Memory& memory;
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public:
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explicit CPU(Memory& mem) : memory(mem) {}
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void Init() {}
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void Init() { memory.ClearMemory(); }
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uint8_t ReadByte(uint16_t address) const override;
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uint16_t ReadWord(uint16_t address) const override;
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uint32_t ReadWordLong(uint16_t address) const override;
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void WriteByte(uint32_t address, uint8_t value) override;
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void WriteWord(uint32_t address, uint16_t value) override;
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void SetMemory(const std::vector<uint8_t>& data) override {
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memory.SetMemory(data);
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}
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int16_t SP() const override { return memory.SP(); }
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void SetSP(int16_t value) override { memory.SetSP(value); }
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uint8_t FetchByte();
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uint16_t FetchWord();
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@@ -115,37 +35,217 @@ class CPU : public Memory {
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uint8_t FetchByteDirectPage(uint8_t operand);
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uint16_t DirectPageIndexedIndirectX();
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uint16_t StackRelative();
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uint16_t DirectPage();
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uint16_t DirectPageIndirectLong();
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uint16_t Immediate();
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uint16_t Absolute();
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uint16_t AbsoluteLong();
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uint16_t DirectPageIndirectIndexedY();
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uint16_t DirectPageIndirect();
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uint16_t StackRelativeIndirectIndexedY();
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uint16_t DirectPageIndexedX();
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uint16_t DirectPageIndirectLongIndexedY();
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uint16_t AbsoluteIndexedY();
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uint16_t AbsoluteIndexedX();
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uint16_t AbsoluteLongIndexedX();
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void ExecuteInstruction(uint8_t opcode);
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void loadROM(const std::vector<uint8_t>& rom) {
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// if (rom.size() > memory.size()) {
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// std::cerr << "ROM too large" << std::endl;
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// return;
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// }
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// std::copy(rom.begin(), rom.end(), memory.begin());
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// ==========================================================================
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// Addressing Modes
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// Effective Address:
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// Bank: Data Bank Register if locating data
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// Program Bank Register if transferring control
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// High: Second operand byte
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// Low: First operand byte
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//
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// LDA addr
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uint16_t Absolute() { return FetchWord(); }
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// Effective Address:
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// The Data Bank Register is concatened with the 16-bit operand
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// the 24-bit result is added to the X Index Register
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// based on the emulation mode (16:X=0, 8:X=1)
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//
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// LDA addr, X
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uint16_t AbsoluteIndexedX() { return FetchWord() + X; }
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// Effective Address:
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// The Data Bank Register is concatened with the 16-bit operand
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// the 24-bit result is added to the Y Index Register
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// based on the emulation mode (16:Y=0, 8:Y=1)
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//
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// LDA addr, Y
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uint16_t AbsoluteIndexedY() { return FetchWord() + Y; }
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// Test Me :)
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// Effective Address:
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// Bank: Program Bank Register (PBR)
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// High/low: The Indirect Address
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// Indirect Address: Located in the Program Bank at the sum of
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// the operand double byte and X based on the
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// emulation mode
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// JMP (addr, X)
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uint16_t AbsoluteIndexedIndirect() {
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uint16_t address = FetchWord() + X;
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return memory.ReadWord(address);
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}
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// Effective Address:
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// Bank: Program Bank Register (PBR)
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// High/low: The Indirect Address
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// Indirect Address: Located in Bank Zero, at the operand double byte
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//
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// JMP (addr)
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uint16_t AbsoluteIndirect() {
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uint16_t address = FetchWord();
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return memory.ReadWord(address);
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}
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// Effective Address:
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// Bank/High/Low: The 24-bit Indirect Address
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// Indirect Address: Located in Bank Zero, at the operand double byte
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//
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// JMP [addr]
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uint32_t AbsoluteIndirectLong() {
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uint16_t address = FetchWord();
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return memory.ReadWordLong(address);
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}
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// Effective Address:
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// Bank: Third operand byte
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// High: Second operand byte
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// Low: First operand byte
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//
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// LDA long
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uint16_t AbsoluteLong() { return FetchLong(); }
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// Effective Address:
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// The 24-bit operand is added to X based on the emulation mode
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//
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// LDA long, X
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uint16_t AbsoluteLongIndexedX() { return FetchLong() + X; }
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// Source Effective Address:
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// Bank: Second operand byte
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// High/Low: The 16-bit value in X, if X is 8-bit high byte is 0
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//
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// Destination Effective Address:
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// Bank: First operand byte
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// High/Low: The 16-bit value in Y, if Y is 8-bit high byte is 0
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//
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// Length:
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// The number of bytes to be moved: 16-bit value in Acculumator C plus 1.
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//
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// MVN src, dst
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void BlockMove(uint16_t source, uint16_t dest, uint16_t length) {
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for (int i = 0; i < length; i++) {
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memory.WriteByte(dest + i, memory.ReadByte(source + i));
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}
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}
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// Effective Address:
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// Bank: Zero
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// High/low: Direct Page Register plus operand byte
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//
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// LDA dp
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uint16_t DirectPage() { return FetchByte(); }
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// Effective Address:
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// Bank: Zero
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// High/low: Direct Page Register plus operand byte plus X
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// based on the emulation mode
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//
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// LDA dp, X
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uint16_t DirectPageIndexedX() {
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uint8_t dp = FetchByte();
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return (dp + X) & 0xFF;
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}
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// Effective Address:
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// Bank: Zero
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// High/low: Direct Page Register plus operand byte plus Y
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// based on the emulation mode
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// LDA dp, Y
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uint16_t DirectPageIndexedY() {
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uint8_t dp = FetchByte();
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return (dp + Y) & 0xFF;
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}
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// Effective Address:
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// Bank: Data bank register
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// High/low: The indirect address
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// Indirect Address: Located in the direct page at the sum of the direct page
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// register, the operand byte, and X based on the emulation mode in bank zero.
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//
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// LDA (dp, X)
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uint16_t DirectPageIndexedIndirectX() {
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uint8_t dp = FetchByte();
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return memory.ReadWord((dp + X) & 0xFF);
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}
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// Effective Address:
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// Bank: Data bank register
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// High/low: The 16-bit indirect address
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// Indirect Address: The operand byte plus the direct page register in bank
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// zero.
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//
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// LDA (dp)
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uint16_t DirectPageIndirect() {
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uint8_t dp = FetchByte();
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return memory.ReadWord(dp);
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}
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// Effective Address:
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// Bank/High/Low: The 24-bit indirect address
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// Indirect address: The operand byte plus the direct page
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// register in bank zero.
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//
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// LDA [dp]
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uint16_t DirectPageIndirectLong() {
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uint8_t dp = FetchByte();
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return memory.ReadWordLong(dp);
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}
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// Effective Address:
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// Found by concatenating the data bank to the double-byte
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// indirect address, then adding Y based on the emulation mode.
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//
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// Indirect Address: Located in the Direct Page at the sum of the direct page
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// register and the operand byte, in bank zero.
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//
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// LDA (dp), Y
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uint16_t DirectPageIndirectIndexedY() {
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uint8_t dp = FetchByte();
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return memory.ReadWord(dp) + Y;
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}
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// Effective Address:
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// Found by adding to the triple-byte indirect address Y based on the
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// emulation mode. Indrect Address: Located in the Direct Page at the sum
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// of the direct page register and the operand byte in bank zero.
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// Indirect Address:
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// Located in the Direct Page at the sum of the direct page register and
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// the operand byte in bank zero.
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//
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// LDA (dp), Y
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uint16_t DirectPageIndirectLongIndexedY() {
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uint8_t dp = FetchByte();
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return memory.ReadWordLong(dp) + Y;
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}
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// 8-bit data: Data Operand Byte
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// 16-bit data 65816 native mode m or x = 0
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// Data High: Second Operand Byte
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// Data Low: First Operand Byte
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//
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// LDA #const
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uint16_t Immediate() { return PC++; }
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uint16_t StackRelative() {
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uint8_t sr = FetchByte();
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return SP() + sr;
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}
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uint16_t StackRelativeIndirectIndexedY() {
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uint8_t sr = FetchByte();
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return memory.ReadWord(SP() + sr) + Y;
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}
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// ==========================================================================
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// Registers
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uint8_t A = 0; // Accumulator
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uint8_t X = 0; // X index register
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uint8_t Y = 0; // Y index register
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uint8_t SP = 0; // Stack Pointer
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uint8_t A = 0; // Accumulator
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uint8_t X = 0; // X index register
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uint8_t Y = 0; // Y index register
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// uint8_t SP = 0; // Stack Pointer
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uint16_t DB = 0; // Data Bank register
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uint16_t D = 0; // Direct Page register
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uint16_t PB = 0; // Program Bank register
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@@ -165,8 +265,8 @@ class CPU : public Memory {
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// B #$10 00010000 Break (emulation mode only)
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// Setting flags in the status register
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int GetAccumulatorSize() { return status & 0x20; }
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int GetIndexSize() { return status & 0x10; }
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int GetAccumulatorSize() const { return status & 0x20; }
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int GetIndexSize() const { return status & 0x10; }
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// Set individual flags
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void SetNegativeFlag(bool set) { SetFlag(0x80, set); }
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@@ -186,7 +286,84 @@ class CPU : public Memory {
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bool GetZeroFlag() const { return GetFlag(0x02); }
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bool GetCarryFlag() const { return GetFlag(0x01); }
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// ==========================================================================
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// Instructions
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// Left to implement
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// * = in progress
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// ADC: Add with carry *
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// AND: Logical AND *
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// ASL: Arithmetic shift left
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// BCC: Branch if carry clear *
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// BCS: Branch if carry set *
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// BEQ: Branch if equal (zero set) *
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// BIT: Bit test
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// BMI: Branch if minus (negative set)
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// BNE: Branch if not equal (zero clear)
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// BPL: Branch if plus (negative clear)
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// BRA: Branch always
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// BRK: Break
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// BRL: Branch always long
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// BVC: Branch if overflow clear
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// BVS: Branch if overflow set
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// CMP: Compare
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// COP: Coprocessor
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// CPX: Compare X register
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// CPY: Compare Y register
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// DEC: Decrement
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// DEX: Decrement X register
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// DEY: Decrement Y register
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// EOR: Exclusive OR
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// INC: Increment
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// INX: Increment X register
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// INY: Increment Y register
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// JMP: Jump
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// JML: Jump long
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// JSR: Jump to subroutine
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// JSL: Jump to subroutine long
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// LDA: Load accumulator
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// LDX: Load X register
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// LDY: Load Y register
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// LSR: Logical shift right
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// MVN: Move negative
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// MVP: Move positive
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// NOP: No operation
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// ORA: Logical OR
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// PEA: Push effective address
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// PEI: Push effective indirect address
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// PER: Push effective PC-relative address
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// PHA: Push accumulator
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// PHB: Push data bank register
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// PHD: Push direct page register
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// PHK: Push program bank register
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// PHP: Push processor status register
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// PHX: Push X register
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// PHY: Push Y register
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// PLA: Pull accumulator
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// PLB: Pull data bank register
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// PLD: Pull direct page register
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// PLP: Pull processor status register
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// PLX: Pull X register
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// PLY: Pull Y register
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// ROL: Rotate left
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// ROR: Rotate right
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// RTI: Return from interrupt
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// RTL: Return from subroutine long
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// RTS: Return from subroutine
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// SBC: Subtract with carry
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// STA: Store accumulator
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// STP: Stop the clock
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// STX: Store X register
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// STY: Store Y register
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// STZ: Store zero
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// TDC: Transfer direct page register to accumulator
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// TRB: Test and reset bits
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// TSB: Test and set bits
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// WAI: Wait for interrupt
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// XBA: Exchange B and A accumulator
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// XCE: Exchange carry and emulation
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void ADC(uint8_t operand);
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void AND(uint16_t address);
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@@ -223,6 +400,18 @@ class CPU : public Memory {
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void CLV() { status &= ~0x40; }
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void PHA() { memory.PushByte(A); }
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void PLA() {
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A = memory.PopByte();
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SetNegativeFlag((A & 0x80) != 0);
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SetZeroFlag(A == 0);
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}
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void PHP() { memory.PushByte(status); }
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void PLP() { status = memory.PopByte(); }
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void SEI() { status |= 0x04; }
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void SED() { status |= 0x08; }
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@@ -251,7 +440,7 @@ class CPU : public Memory {
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SetNegativeFlag(A & 0x80);
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}
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void TCS() { SP = A; }
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void TCS() { memory.SetSP(A); }
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void TAX() {
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X = A;
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@@ -290,15 +479,15 @@ class CPU : public Memory {
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}
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void TSX() {
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X = SP;
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X = SP();
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SetZeroFlag(X == 0);
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SetNegativeFlag(X & 0x80);
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}
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void TXS() { SP = X; }
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void TXS() { memory.SetSP(X); }
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void TSC() {
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A = SP;
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A = SP();
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SetZeroFlag(A == 0);
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SetNegativeFlag(A & 0x80);
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}
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@@ -328,14 +517,19 @@ class CPU : public Memory {
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// Helper function to get the value of a specific flag bit
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bool GetFlag(uint8_t mask) const { return (status & mask) != 0; }
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// Appease the C++ Gods...
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void PushByte(uint8_t value) override { memory.PushByte(value); }
|
||||
void PushWord(uint16_t value) override { memory.PushWord(value); }
|
||||
uint8_t PopByte() override { return memory.PopByte(); }
|
||||
uint16_t PopWord() override { return memory.PopWord(); }
|
||||
void ClearMemory() override { memory.ClearMemory(); }
|
||||
void LoadData(const std::vector<uint8_t>& data) override {
|
||||
memory.LoadData(data);
|
||||
}
|
||||
|
||||
// Appease the C++ Gods...
|
||||
uint8_t operator[](int i) const override { return 0; }
|
||||
uint8_t at(int i) const override { return 0; }
|
||||
|
||||
Memory& memory;
|
||||
};
|
||||
|
||||
} // namespace emu
|
||||
|
||||
Reference in New Issue
Block a user