feat: Refactor Emulator to Accept ROM Parameter and Enhance Logging
- Updated Emulator::Run method to accept a Rom* parameter, improving flexibility in ROM handling. - Refactored texture creation and ROM data initialization to utilize the new parameter. - Enhanced logging in Snes class to provide detailed information during initialization, reset, and frame processing, aiding in debugging and performance monitoring. - Introduced cycle tracking in Apu and Spc700 classes for accurate synchronization and debugging. - Added unit tests for APU DSP functionality and IPL ROM handshake to ensure reliability and correctness of audio processing.
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scawful
@@ -8,6 +8,7 @@
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#include "app/emu/audio/dsp.h"
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#include "app/emu/audio/spc700.h"
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#include "app/emu/memory/memory.h"
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#include "util/log.h"
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namespace yaze {
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namespace emu {
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@@ -15,38 +16,38 @@ namespace emu {
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static const double apuCyclesPerMaster = (32040 * 32) / (1364 * 262 * 60.0);
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static const double apuCyclesPerMasterPal = (32040 * 32) / (1364 * 312 * 50.0);
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// Standard SNES IPL ROM (64 bytes at $FFC0-$FFFF)
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// Verified correct - matches hardware dumps
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static const uint8_t bootRom[0x40] = {
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0xcd, 0xef, 0xbd, 0xe8, 0x00, 0xc6, 0x1d, 0xd0, 0xfc, 0x8f, 0xaa,
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0xf4, 0x8f, 0xbb, 0xf5, 0x78, 0xcc, 0xf4, 0xd0, 0xfb, 0x2f, 0x19,
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0xeb, 0xf4, 0xd0, 0xfc, 0x7e, 0xf4, 0xd0, 0x0b, 0xe4, 0xf5, 0xcb,
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0xf4, 0xd7, 0x00, 0xfc, 0xd0, 0xf3, 0xab, 0x01, 0x10, 0xef, 0x7e,
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0xf4, 0x10, 0xeb, 0xba, 0xf6, 0xda, 0x00, 0xba, 0xf4, 0xc4, 0xf4,
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0xdd, 0x5d, 0xd0, 0xdb, 0x1f, 0x00, 0x00, 0xc0, 0xff};
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0xf4, 0x8f, 0xbb, 0xf5, 0xe4, 0xf4, 0x68, 0xcc, 0xd0, 0xfa, 0x2f,
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0x19, 0xeb, 0xf4, 0xd0, 0xfc, 0x7e, 0xf4, 0xd0, 0x0b, 0xe4, 0xf5,
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0xcb, 0xf4, 0xd7, 0x00, 0xfc, 0xd0, 0xf3, 0xab, 0x01, 0x10, 0xef,
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0x7e, 0xf4, 0x10, 0xeb, 0xba, 0xf6, 0xda, 0x00, 0xba, 0xf4, 0xc4,
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0xf4, 0xdd, 0x5d, 0xd0, 0xdb, 0x1f, 0x00, 0xc0, 0xff};
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// Helper to reset the cycle tracking on emulator reset
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static uint64_t g_last_master_cycles = 0;
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static void ResetCycleTracking() { g_last_master_cycles = 0; }
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void Apu::Init() {
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ram.resize(0x10000);
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for (int i = 0; i < 0x10000; i++) {
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ram[i] = 0;
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}
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// Copy the boot rom into the ram at ffc0
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for (int i = 0; i < 0x40; i++) {
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ram[0xffc0 + i] = bootRom[i];
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}
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}
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void Apu::Reset() {
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LOG_INFO("APU", "Reset called");
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spc700_.Reset(true);
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dsp_.Reset();
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for (int i = 0; i < 0x10000; i++) {
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ram[i] = 0;
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}
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// Copy the boot rom into the ram at ffc0
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for (int i = 0; i < 0x40; i++) {
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ram[0xffc0 + i] = bootRom[i];
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}
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rom_readable_ = true;
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dsp_adr_ = 0;
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cycles_ = 0;
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ResetCycleTracking(); // Reset the master cycle delta tracking
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std::fill(in_ports_.begin(), in_ports_.end(), 0);
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std::fill(out_ports_.begin(), out_ports_.end(), 0);
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for (int i = 0; i < 3; i++) {
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@@ -56,15 +57,59 @@ void Apu::Reset() {
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timer_[i].counter = 0;
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timer_[i].enabled = false;
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}
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LOG_INFO("APU", "Reset complete - IPL ROM readable, PC will be at $%04X",
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spc700_.read_word(0xFFFE));
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}
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void Apu::RunCycles(uint64_t cycles) {
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uint64_t sync_to =
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(uint64_t)cycles *
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(memory_.pal_timing() ? apuCyclesPerMasterPal : apuCyclesPerMaster);
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void Apu::RunCycles(uint64_t master_cycles) {
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// Convert CPU master cycles to APU cycles target and step SPC/DSP accordingly.
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const double ratio = memory_.pal_timing() ? apuCyclesPerMasterPal : apuCyclesPerMaster;
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// Track last master cycles to only advance by the delta
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uint64_t master_delta = master_cycles - g_last_master_cycles;
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g_last_master_cycles = master_cycles;
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const uint64_t target_apu_cycles = cycles_ + static_cast<uint64_t>(master_delta * ratio);
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while (cycles_ < sync_to) {
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// Watchdog to detect infinite loops
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static uint64_t last_log_cycle = 0;
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static uint16_t last_pc = 0;
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static int stuck_counter = 0;
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while (cycles_ < target_apu_cycles) {
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// Execute one SPC700 opcode (variable cycles) then advance APU cycles accordingly.
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uint16_t current_pc = spc700_.PC;
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// Detect if SPC is stuck in tight loop
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if (current_pc == last_pc) {
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stuck_counter++;
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if (stuck_counter > 10000 && cycles_ - last_log_cycle > 10000) {
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LOG_WARN("APU", "SPC700 stuck at PC=$%04X for %d iterations",
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current_pc, stuck_counter);
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LOG_WARN("APU", "Port Status: F4=$%02X F5=$%02X F6=$%02X F7=$%02X",
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in_ports_[0], in_ports_[1], in_ports_[2], in_ports_[3]);
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LOG_WARN("APU", "Out Ports: F4=$%02X F5=$%02X F6=$%02X F7=$%02X",
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out_ports_[0], out_ports_[1], out_ports_[2], out_ports_[3]);
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LOG_WARN("APU", "IPL ROM enabled: %s", rom_readable_ ? "YES" : "NO");
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last_log_cycle = cycles_;
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stuck_counter = 0;
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}
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} else {
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stuck_counter = 0;
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}
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last_pc = current_pc;
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spc700_.RunOpcode();
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// Get the actual cycle count from the last opcode execution
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// This is critical for proper IPL ROM handshake timing
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int spc_cycles = spc700_.GetLastOpcodeCycles();
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// Advance APU cycles based on actual SPC700 opcode timing
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// The SPC700 runs at 1.024 MHz, and we need to synchronize with the DSP/timers
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for (int i = 0; i < spc_cycles; ++i) {
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Cycle();
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}
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}
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}
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@@ -94,6 +139,7 @@ void Apu::Cycle() {
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}
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uint8_t Apu::Read(uint16_t adr) {
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static int port_read_count = 0;
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switch (adr) {
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case 0xf0:
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case 0xf1:
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@@ -111,10 +157,19 @@ uint8_t Apu::Read(uint16_t adr) {
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case 0xf4:
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case 0xf5:
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case 0xf6:
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case 0xf7:
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case 0xf7: {
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uint8_t val = in_ports_[adr - 0xf4];
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port_read_count++;
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if (port_read_count < 100) { // Increased limit to see full handshake
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LOG_INFO("APU", "SPC read port $%04X (F%d) = $%02X at PC=$%04X",
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adr, adr - 0xf4 + 4, val, spc700_.PC);
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}
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return val;
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}
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case 0xf8:
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case 0xf9: {
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return in_ports_[adr - 0xf4];
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// Not I/O ports on real hardware; treat as general RAM region.
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return ram[adr];
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}
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case 0xfd:
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case 0xfe:
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@@ -131,11 +186,18 @@ uint8_t Apu::Read(uint16_t adr) {
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}
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void Apu::Write(uint16_t adr, uint8_t val) {
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static int port_write_count = 0;
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// Debug: Log ALL writes to F4 to diagnose missing echo
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static int f4_write_count = 0;
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if (adr == 0xF4 && f4_write_count++ < 10) {
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LOG_INFO("APU", "Write() called for $F4 = $%02X at PC=$%04X", val, spc700_.PC);
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}
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switch (adr) {
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case 0xf0: {
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break; // test register
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}
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case 0xf1: {
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bool old_rom_readable = rom_readable_;
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for (int i = 0; i < 3; i++) {
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if (!timer_[i].enabled && (val & (1 << i))) {
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timer_[i].divider = 0;
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@@ -151,7 +213,12 @@ void Apu::Write(uint16_t adr, uint8_t val) {
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in_ports_[2] = 0;
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in_ports_[3] = 0;
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}
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rom_readable_ = val & 0x80;
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// IPL ROM mapping: initially enabled; writing 1 to bit7 disables IPL ROM.
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rom_readable_ = (val & 0x80) == 0;
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if (old_rom_readable != rom_readable_) {
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LOG_INFO("APU", "Control register $F1 = $%02X - IPL ROM %s at PC=$%04X",
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val, rom_readable_ ? "ENABLED" : "DISABLED", spc700_.PC);
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}
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break;
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}
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case 0xf2: {
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@@ -167,11 +234,16 @@ void Apu::Write(uint16_t adr, uint8_t val) {
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case 0xf6:
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case 0xf7: {
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out_ports_[adr - 0xf4] = val;
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port_write_count++;
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if (port_write_count < 100) { // Increased limit to see full handshake
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LOG_INFO("APU", "SPC wrote port $%04X (F%d) = $%02X at PC=$%04X [APU_cycles=%llu]",
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adr, adr - 0xf4 + 4, val, spc700_.PC, cycles_);
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}
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break;
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}
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case 0xf8:
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case 0xf9: {
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in_ports_[adr - 0xf4] = val;
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// General RAM
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break;
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}
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case 0xfa:
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