154 lines
4.2 KiB
C++
154 lines
4.2 KiB
C++
#include <gtest/gtest.h>
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#include "app/emu/audio/apu.h"
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#include "app/emu/memory/memory.h"
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#include "app/emu/audio/spc700.h"
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namespace yaze {
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namespace emu {
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class ApuIplHandshakeTest : public ::testing::Test {
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protected:
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MemoryImpl mem;
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Apu* apu;
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void SetUp() override {
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std::vector<uint8_t> dummy_rom(0x200000, 0);
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mem.Initialize(dummy_rom);
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apu = new Apu(mem);
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apu->Init();
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apu->Reset();
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}
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void TearDown() override { delete apu; }
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};
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TEST_F(ApuIplHandshakeTest, SPC700StartsAtIplRomEntry) {
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// After reset, PC should be at IPL ROM reset vector
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uint16_t reset_vector = apu->spc700().read(0xFFFE) |
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(apu->spc700().read(0xFFFF) << 8);
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// The IPL ROM reset vector should point to 0xFFC0 (start of IPL ROM)
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EXPECT_EQ(reset_vector, 0xFFC0);
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}
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TEST_F(ApuIplHandshakeTest, IplRomReadable) {
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// IPL ROM should be readable at 0xFFC0-0xFFFF after reset
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uint8_t first_byte = apu->Read(0xFFC0);
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// First byte of IPL ROM should be 0xCD (CMP Y, #$EF)
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EXPECT_EQ(first_byte, 0xCD);
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}
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TEST_F(ApuIplHandshakeTest, CycleTrackingWorks) {
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// Execute one SPC700 opcode
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apu->spc700().RunOpcode();
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// GetLastOpcodeCycles should return a valid cycle count (2-12 typically)
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int cycles = apu->spc700().GetLastOpcodeCycles();
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EXPECT_GT(cycles, 0);
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EXPECT_LE(cycles, 12);
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}
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TEST_F(ApuIplHandshakeTest, PortReadWrite) {
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// Write to input port from CPU side (simulating CPU writes to $2140-$2143)
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apu->in_ports_[0] = 0xAA;
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apu->in_ports_[1] = 0xBB;
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// SPC should be able to read these ports at $F4-$F7
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EXPECT_EQ(apu->Read(0xF4), 0xAA);
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EXPECT_EQ(apu->Read(0xF5), 0xBB);
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// Write to output ports from SPC side
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apu->Write(0xF4, 0xCC);
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apu->Write(0xF5, 0xDD);
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// CPU should be able to read these (simulating reads from $2140-$2143)
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EXPECT_EQ(apu->out_ports_[0], 0xCC);
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EXPECT_EQ(apu->out_ports_[1], 0xDD);
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}
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TEST_F(ApuIplHandshakeTest, IplRomDisableViaControlRegister) {
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// IPL ROM is readable by default
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EXPECT_EQ(apu->Read(0xFFC0), 0xCD);
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// Write to control register ($F1) to disable IPL ROM (bit 7 = 1)
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apu->Write(0xF1, 0x80);
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// Now $FFC0-$FFFF should read from RAM instead of IPL ROM
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// RAM is initialized to 0, so we should read 0
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EXPECT_EQ(apu->Read(0xFFC0), 0x00);
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// Write something to RAM
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apu->ram[0xFFC0] = 0x42;
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EXPECT_EQ(apu->Read(0xFFC0), 0x42);
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// Re-enable IPL ROM (bit 7 = 0)
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apu->Write(0xF1, 0x00);
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// Should read IPL ROM again
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EXPECT_EQ(apu->Read(0xFFC0), 0xCD);
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}
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TEST_F(ApuIplHandshakeTest, TimersEnableAndCount) {
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// Enable timer 0 via control register
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apu->Write(0xF1, 0x01);
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// Set timer 0 target to 4
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apu->Write(0xFA, 0x04);
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// Run enough cycles to trigger timer
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for (int i = 0; i < 1000; ++i) {
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apu->Cycle();
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}
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// Read timer 0 counter (auto-clears on read)
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uint8_t counter = apu->Read(0xFD);
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// Counter should be non-zero if timer is working
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EXPECT_GT(counter, 0);
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EXPECT_LE(counter, 0x0F);
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}
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TEST_F(ApuIplHandshakeTest, IplBootSequenceProgresses) {
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// This test verifies that the IPL ROM boot sequence can actually progress
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// without getting stuck in an infinite loop
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uint16_t initial_pc = apu->spc700().PC;
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// Run multiple opcodes to let the IPL boot sequence progress
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for (int i = 0; i < 100; ++i) {
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apu->spc700().RunOpcode();
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apu->Cycle();
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}
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uint16_t final_pc = apu->spc700().PC;
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// PC should have advanced (boot sequence is progressing)
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// If it's stuck in a tight loop, PC won't change much
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EXPECT_NE(initial_pc, final_pc);
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}
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TEST_F(ApuIplHandshakeTest, AccurateCycleCountsForCommonOpcodes) {
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// Test that specific opcodes return correct cycle counts
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// NOP (0x00) should take 2 cycles
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apu->spc700().PC = 0x0000;
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apu->ram[0x0000] = 0x00; // NOP
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apu->spc700().RunOpcode();
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apu->spc700().RunOpcode(); // Execute
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EXPECT_EQ(apu->spc700().GetLastOpcodeCycles(), 2);
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// MOV A, #imm (0xE8) should take 2 cycles
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apu->spc700().PC = 0x0002;
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apu->ram[0x0002] = 0xE8; // MOV A, #imm
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apu->ram[0x0003] = 0x42; // immediate value
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apu->spc700().RunOpcode();
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apu->spc700().RunOpcode();
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EXPECT_EQ(apu->spc700().GetLastOpcodeCycles(), 2);
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}
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} // namespace emu
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} // namespace yaze
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