3734884ba3
- Updated Snes constructor to initialize CPU callbacks directly, improving readability and maintainability. - Removed unnecessary CpuCallbacks parameter from Cpu constructor, streamlining the class design. - Added new methods in Apu for retrieving cycles, status, control, and handling DMA transfers, enhancing audio processing capabilities. - Introduced unit tests for Apu to validate initialization, sample generation, and handshake timing, ensuring robust audio functionality.
134 lines
3.4 KiB
C++
134 lines
3.4 KiB
C++
#include "app/emu/audio/apu.h"
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#include "app/emu/memory/memory.h"
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#include <gmock/gmock-nice-strict.h>
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#include <gmock/gmock.h>
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#include <gtest/gtest.h>
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namespace yaze {
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namespace test {
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using testing::_;
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using testing::Return;
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using yaze::emu::Apu;
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using yaze::emu::MemoryImpl;
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class ApuTest : public ::testing::Test {
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protected:
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void SetUp() override {
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memory_ = std::make_unique<MemoryImpl>();
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apu_ = std::make_unique<Apu>(*memory_);
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apu_->Init();
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}
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std::unique_ptr<MemoryImpl> memory_;
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std::unique_ptr<Apu> apu_;
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};
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// Test the IPL ROM handshake sequence timing
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TEST_F(ApuTest, IplRomHandshakeTiming) {
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// 1. Initial state check
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EXPECT_EQ(apu_->Read(0x00) & 0x80, 0); // Ready bit should be clear
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// 2. Start handshake
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apu_->Write(0x00, 0x80); // Set control register bit 7
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// 3. Wait for APU ready signal with cycle counting
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int cycles = 0;
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const int max_cycles = 1000; // Maximum expected cycles for handshake
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while (!(apu_->Read(0x00) & 0x80) && cycles < max_cycles) {
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apu_->RunCycles(1);
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cycles++;
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}
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// 4. Verify timing constraints
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EXPECT_LT(cycles, max_cycles); // Should complete within max cycles
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EXPECT_GT(cycles, 0); // Should take some cycles
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EXPECT_TRUE(apu_->Read(0x00) & 0x80); // Ready bit should be set
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// 5. Verify handshake completion
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EXPECT_EQ(apu_->GetStatus() & 0x80, 0x80); // Ready bit in status register
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}
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// Test APU initialization sequence
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TEST_F(ApuTest, ApuInitialization) {
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// 1. Check initial state
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EXPECT_EQ(apu_->GetStatus(), 0x00);
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EXPECT_EQ(apu_->GetControl(), 0x00);
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// 2. Initialize APU
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apu_->Init();
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// 3. Verify initialization
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EXPECT_EQ(apu_->GetStatus(), 0x00);
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EXPECT_EQ(apu_->GetControl(), 0x00);
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// 4. Check DSP registers are initialized
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for (int i = 0; i < 128; i++) {
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EXPECT_EQ(apu_->Read(0x00 + i), 0x00);
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}
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}
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// Test sample generation and timing
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TEST_F(ApuTest, SampleGenerationTiming) {
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// 1. Generate samples
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const int sample_count = 1024;
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std::vector<int16_t> samples(sample_count);
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// 2. Measure timing
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uint64_t start_cycles = apu_->GetCycles();
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apu_->GetSamples(samples.data(), sample_count, false);
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uint64_t end_cycles = apu_->GetCycles();
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// 3. Verify timing
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EXPECT_GT(end_cycles - start_cycles, 0);
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// 4. Verify samples
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bool has_non_zero = false;
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for (int i = 0; i < sample_count; ++i) {
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if (samples[i] != 0) {
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has_non_zero = true;
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break;
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}
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}
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EXPECT_TRUE(has_non_zero);
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}
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// Test DSP register access timing
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TEST_F(ApuTest, DspRegisterAccessTiming) {
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// 1. Write to DSP registers
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const uint8_t test_value = 0x42;
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uint64_t start_cycles = apu_->GetCycles();
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apu_->Write(0x00, 0x80); // Set control register
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apu_->Write(0x01, test_value); // Write to DSP address
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uint64_t end_cycles = apu_->GetCycles();
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// 2. Verify timing
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EXPECT_GT(end_cycles - start_cycles, 0);
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// 3. Verify register access
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EXPECT_EQ(apu_->Read(0x01), test_value);
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}
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// Test DMA transfer timing
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TEST_F(ApuTest, DmaTransferTiming) {
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// 1. Prepare DMA data
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const uint8_t data[] = {0x01, 0x02, 0x03, 0x04};
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// 2. Measure DMA timing
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uint64_t start_cycles = apu_->GetCycles();
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apu_->WriteDma(0x00, data, sizeof(data));
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uint64_t end_cycles = apu_->GetCycles();
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// 3. Verify timing
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EXPECT_GT(end_cycles - start_cycles, 0);
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// 4. Verify DMA transfer
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EXPECT_EQ(apu_->Read(0x00), 0x01);
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EXPECT_EQ(apu_->Read(0x01), 0x02);
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}
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} // namespace test
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} // namespace yaze
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