overhaul memory, manage open bus, pal timing, v_pos, h_pos, cartridges, dma channels
This commit is contained in:
scawful
@@ -14,6 +14,215 @@ namespace app {
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namespace emu {
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namespace memory {
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void MemoryImpl::Initialize(const std::vector<uint8_t>& romData, bool verbose) {
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verbose_ = verbose;
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auto location = 0x7FC0; // GetHeaderOffset();
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romSize = 0x400 << romData[location + 0x17];
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sramSize = 0x400 << romData[location + 0x18];
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rom_.resize(romSize);
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// Copy memory into rom_
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std::copy(romData.begin() + kROMStart, romData.begin() + kROMStart + kROMSize,
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rom_.begin());
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memory_.resize(0x1000000); // 16 MB
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const size_t ROM_CHUNK_SIZE = 0x8000; // 32 KB
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// Clear memory
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std::fill(memory_.begin(), memory_.end(), 0);
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// Load ROM data into memory based on LoROM mapping
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size_t romSize = romData.size();
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size_t romAddress = 0;
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for (size_t bank = 0x00; bank <= 0x3F; ++bank) {
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for (size_t offset = 0x8000; offset <= 0xFFFF; offset += ROM_CHUNK_SIZE) {
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if (romAddress < romSize) {
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std::copy(romData.begin() + romAddress,
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romData.begin() + romAddress + ROM_CHUNK_SIZE,
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memory_.begin() + (bank << 16) + offset);
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romAddress += ROM_CHUNK_SIZE;
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}
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}
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}
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// Copy data into rom_ vector
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rom_.resize(kROMSize);
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std::copy(memory_.begin() + kROMStart, memory_.begin() + kROMStart + kROMSize,
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rom_.begin());
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// Copy data into ram_ vector
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ram_.resize(kRAMSize);
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std::copy(memory_.begin() + kRAMStart, memory_.begin() + kRAMStart + kRAMSize,
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ram_.begin());
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}
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memory::RomInfo MemoryImpl::ReadRomHeader() {
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memory::RomInfo romInfo;
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uint32_t offset = GetHeaderOffset();
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// Read cartridge title
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char title[22];
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for (int i = 0; i < 21; ++i) {
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title[i] = ReadByte(offset + i);
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}
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title[21] = '\0'; // Null-terminate the string
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romInfo.title = std::string(title);
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// Read ROM speed and memory map mode
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uint8_t romSpeedAndMapMode = ReadByte(offset + 0x15);
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romInfo.romSpeed = (memory::RomSpeed)(romSpeedAndMapMode & 0x07);
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romInfo.bankSize = (memory::BankSize)((romSpeedAndMapMode >> 5) & 0x01);
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// Read ROM type
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romInfo.romType = (memory::RomType)ReadByte(offset + 0x16);
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// Read ROM size
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romInfo.romSize = (memory::RomSize)ReadByte(offset + 0x17);
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// Read RAM size
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romInfo.sramSize = (memory::SramSize)ReadByte(offset + 0x18);
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// Read country code
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romInfo.countryCode = (memory::CountryCode)ReadByte(offset + 0x19);
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// Read license
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romInfo.license = (memory::License)ReadByte(offset + 0x1A);
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// Read ROM version
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romInfo.version = ReadByte(offset + 0x1B);
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// Read checksum complement
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romInfo.checksumComplement = ReadWord(offset + 0x1E);
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// Read checksum
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romInfo.checksum = ReadWord(offset + 0x1C);
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// Read NMI VBL vector
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romInfo.nmiVblVector = ReadWord(offset + 0x3E);
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// Read reset vector
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romInfo.resetVector = ReadWord(offset + 0x3C);
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return romInfo;
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}
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uint8_t MemoryImpl::cart_read(uint8_t bank, uint16_t adr) {
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switch (type_) {
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case 0:
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return open_bus_;
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case 1:
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return cart_readLorom(bank, adr);
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case 2:
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return cart_readHirom(bank, adr);
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case 3:
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return cart_readExHirom(bank, adr);
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}
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return open_bus_;
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}
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void MemoryImpl::cart_write(uint8_t bank, uint16_t adr, uint8_t val) {
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switch (type_) {
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case 0:
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break;
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case 1:
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cart_writeLorom(bank, adr, val);
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break;
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case 2:
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cart_writeHirom(bank, adr, val);
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break;
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case 3:
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cart_writeHirom(bank, adr, val);
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break;
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}
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}
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uint8_t MemoryImpl::cart_readLorom(uint8_t bank, uint16_t adr) {
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if (((bank >= 0x70 && bank < 0x7e) || bank >= 0xf0) && adr < 0x8000 &&
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sramSize > 0) {
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// banks 70-7e and f0-ff, adr 0000-7fff
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return ram_[(((bank & 0xf) << 15) | adr) & (sramSize - 1)];
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}
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bank &= 0x7f;
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if (adr >= 0x8000 || bank >= 0x40) {
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// adr 8000-ffff in all banks or all addresses in banks 40-7f and c0-ff
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return rom_[((bank << 15) | (adr & 0x7fff)) & (romSize - 1)];
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}
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return open_bus_;
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}
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void MemoryImpl::cart_writeLorom(uint8_t bank, uint16_t adr, uint8_t val) {
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if (((bank >= 0x70 && bank < 0x7e) || bank > 0xf0) && adr < 0x8000 &&
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sramSize > 0) {
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// banks 70-7e and f0-ff, adr 0000-7fff
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ram_[(((bank & 0xf) << 15) | adr) & (sramSize - 1)] = val;
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}
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}
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uint8_t MemoryImpl::cart_readHirom(uint8_t bank, uint16_t adr) {
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bank &= 0x7f;
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if (bank < 0x40 && adr >= 0x6000 && adr < 0x8000 && sramSize > 0) {
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// banks 00-3f and 80-bf, adr 6000-7fff
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return ram_[(((bank & 0x3f) << 13) | (adr & 0x1fff)) & (sramSize - 1)];
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}
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if (adr >= 0x8000 || bank >= 0x40) {
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// adr 8000-ffff in all banks or all addresses in banks 40-7f and c0-ff
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return rom_[(((bank & 0x3f) << 16) | adr) & (romSize - 1)];
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}
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return open_bus_;
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}
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uint8_t MemoryImpl::cart_readExHirom(uint8_t bank, uint16_t adr) {
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if ((bank & 0x7f) < 0x40 && adr >= 0x6000 && adr < 0x8000 && sramSize > 0) {
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// banks 00-3f and 80-bf, adr 6000-7fff
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return ram_[(((bank & 0x3f) << 13) | (adr & 0x1fff)) & (sramSize - 1)];
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}
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bool secondHalf = bank < 0x80;
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bank &= 0x7f;
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if (adr >= 0x8000 || bank >= 0x40) {
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// adr 8000-ffff in all banks or all addresses in banks 40-7f and c0-ff
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return rom_[(((bank & 0x3f) << 16) | (secondHalf ? 0x400000 : 0) | adr) &
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(romSize - 1)];
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}
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return open_bus_;
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}
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void MemoryImpl::cart_writeHirom(uint8_t bank, uint16_t adr, uint8_t val) {
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bank &= 0x7f;
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if (bank < 0x40 && adr >= 0x6000 && adr < 0x8000 && sramSize > 0) {
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// banks 00-3f and 80-bf, adr 6000-7fff
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ram_[(((bank & 0x3f) << 13) | (adr & 0x1fff)) & (sramSize - 1)] = val;
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}
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}
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uint32_t MemoryImpl::GetMappedAddress(uint32_t address) const {
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uint8_t bank = address >> 16;
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uint32_t offset = address & 0xFFFF;
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if (bank <= 0x3F) {
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if (address <= 0x1FFF) {
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return (0x7E << 16) + offset; // Shadow RAM
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} else if (address <= 0x5FFF) {
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return (bank << 16) + (offset - 0x2000) + 0x2000; // Hardware Registers
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} else if (address <= 0x7FFF) {
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return offset - 0x6000 + 0x6000; // Expansion RAM
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} else {
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// Return lorom mapping
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return (bank << 16) + (offset - 0x8000) + 0x8000; // ROM
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}
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} else if (bank == 0x7D) {
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return offset + 0x7D0000; // SRAM
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} else if (bank == 0x7E || bank == 0x7F) {
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return offset + 0x7E0000; // System RAM
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} else if (bank >= 0x80) {
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// Handle HiROM and mirrored areas
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}
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return address; // Return the original address if no mapping is defined
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}
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void DrawSnesMemoryMapping(const MemoryImpl& memory) {
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// Using those as a base value to create width/height that are factor of the
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// size of our font
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@@ -2,11 +2,13 @@
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#define MEM_H
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#include <cstdint>
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#include <functional>
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#include <iostream>
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#include <string>
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#include <vector>
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#include "app/emu/debug/log.h"
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#include "app/emu/memory/dma_channel.h"
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// LoROM (Mode 20):
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@@ -91,20 +93,16 @@ class RomInfo {
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uint16_t resetVector;
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};
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class Observer {
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public:
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virtual ~Observer() = default;
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virtual void Notify(uint32_t address, uint16_t data) = 0;
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};
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typedef struct CpuCallbacks {
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std::function<uint8_t(uint32_t)> read_byte;
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std::function<void(uint32_t, uint8_t)> write_byte;
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std::function<void(bool waiting)> idle;
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} CpuCallbacks;
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constexpr uint32_t kROMStart = 0x008000;
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constexpr uint32_t kROMSize = 0x200000;
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constexpr uint32_t kRAMStart = 0x7E0000;
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constexpr uint32_t kRAMSize = 0x20000;
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constexpr uint32_t kVRAMStart = 0x210000;
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constexpr uint32_t kVRAMSize = 0x10000;
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constexpr uint32_t kOAMStart = 0x218000;
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constexpr uint32_t kOAMSize = 0x220;
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/**
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* @brief Memory interface
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@@ -136,139 +134,86 @@ class Memory {
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virtual uint8_t operator[](int i) const = 0;
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virtual uint8_t at(int i) const = 0;
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};
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enum class MemoryMapping { SNES_LOROM = 0, PC_ADDRESS = 1 };
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virtual uint8_t open_bus() const = 0;
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virtual void set_open_bus(uint8_t value) = 0;
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virtual bool hdma_init_requested() const = 0;
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virtual bool hdma_run_requested() const = 0;
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virtual void init_hdma_request() = 0;
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virtual void run_hdma_request() = 0;
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virtual void set_hdma_run_requested(bool value) = 0;
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virtual void set_hdma_init_requested(bool value) = 0;
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virtual void set_pal_timing(bool value) = 0;
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virtual void set_h_pos(uint16_t value) = 0;
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virtual void set_v_pos(uint16_t value) = 0;
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// get h_pos and v_pos
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virtual auto h_pos() const -> uint16_t = 0;
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virtual auto v_pos() const -> uint16_t = 0;
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// get pal timing
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virtual auto pal_timing() const -> bool = 0;
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};
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/**
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* @class MemoryImpl
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* @brief Implementation of the Memory interface for emulating memory in a SNES
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* system.
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*
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* The MemoryImpl class provides methods for initializing and accessing memory
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* in a SNES system. It implements the Memory interface and inherits from the
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* Loggable class.
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*
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* The class supports different memory mappings, including LoROM and PC_ADDRESS
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* mappings. It provides methods for reading and writing bytes, words, and longs
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* from/to memory. It also supports stack operations for pushing and popping
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* values.
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*
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* The class maintains separate vectors for ROM, RAM, VRAM, and OAM memory
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* regions. It provides methods for accessing these memory regions and
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* retrieving their sizes.
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*
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* The class also allows adding observers to be notified when memory is read or
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* written.
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*
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* @note This class assumes a 16-bit address space.
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*/
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class MemoryImpl : public Memory, public Loggable {
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public:
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void Initialize(const std::vector<uint8_t>& romData, bool verbose = false,
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MemoryMapping mapping = MemoryMapping::SNES_LOROM) {
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verbose_ = verbose;
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mapping_ = mapping;
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if (mapping == MemoryMapping::PC_ADDRESS) {
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memory_.resize(romData.size());
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std::copy(romData.begin(), romData.end(), memory_.begin());
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return;
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uint32_t romSize;
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uint32_t sramSize;
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void Initialize(const std::vector<uint8_t>& romData, bool verbose = false);
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uint16_t GetHeaderOffset() {
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uint8_t mapMode = rom_[(0x00 << 16) + 0xFFD5];
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uint16_t offset;
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switch (mapMode & 0x07) {
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case 0: // LoROM
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offset = 0x7FC0;
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break;
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case 1: // HiROM
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offset = 0xFFC0;
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break;
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case 5: // ExHiROM
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offset = 0x40;
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break;
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default:
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throw std::invalid_argument(
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"Unable to locate supported ROM mapping mode in the provided ROM "
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"file. Please try another ROM file.");
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}
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memory_.resize(0x1000000); // 16 MB
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const size_t ROM_CHUNK_SIZE = 0x8000; // 32 KB
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const size_t SRAM_SIZE = 0x10000; // 64 KB
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const size_t SYSTEM_RAM_SIZE = 0x20000; // 128 KB
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const size_t EXPANSION_RAM_SIZE = 0x2000; // 8 KB
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const size_t HARDWARE_REGISTERS_SIZE = 0x4000; // 16 KB
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// Clear memory
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std::fill(memory_.begin(), memory_.end(), 0);
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// Load ROM data into memory based on LoROM mapping
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size_t romSize = romData.size();
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size_t romAddress = 0;
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for (size_t bank = 0x00; bank <= 0x3F; ++bank) {
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for (size_t offset = 0x8000; offset <= 0xFFFF; offset += ROM_CHUNK_SIZE) {
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if (romAddress < romSize) {
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std::copy(romData.begin() + romAddress,
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romData.begin() + romAddress + ROM_CHUNK_SIZE,
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memory_.begin() + (bank << 16) + offset);
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romAddress += ROM_CHUNK_SIZE;
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}
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}
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}
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// Initialize SRAM at banks 0x7D and 0xFD
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std::fill(memory_.begin() + (0x7D << 16), memory_.begin() + (0x7E << 16),
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0);
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std::fill(memory_.begin() + (0xFD << 16), memory_.begin() + (0xFE << 16),
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0);
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// Initialize System RAM at banks 0x7E and 0x7F
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std::fill(memory_.begin() + (0x7E << 16),
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memory_.begin() + (0x7E << 16) + SYSTEM_RAM_SIZE, 0);
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// Initialize Shadow RAM at banks 0x00-0x3F and 0x80-0xBF
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for (size_t bank = 0x00; bank <= 0xBF; bank += 0x80) {
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std::fill(memory_.begin() + (bank << 16),
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memory_.begin() + (bank << 16) + 0x2000, 0);
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}
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// Initialize Hardware Registers at banks 0x00-0x3F and 0x80-0xBF
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for (size_t bank = 0x00; bank <= 0xBF; bank += 0x80) {
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std::fill(
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memory_.begin() + (bank << 16) + 0x2000,
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memory_.begin() + (bank << 16) + 0x2000 + HARDWARE_REGISTERS_SIZE, 0);
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}
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// Initialize Expansion RAM at banks 0x00-0x3F and 0x80-0xBF
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for (size_t bank = 0x00; bank <= 0xBF; bank += 0x80) {
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std::fill(memory_.begin() + (bank << 16) + 0x6000,
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memory_.begin() + (bank << 16) + 0x6000 + EXPANSION_RAM_SIZE,
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0);
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}
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// Initialize Reset and NMI Vectors at bank 0xFF
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std::fill(memory_.begin() + (0xFF << 16) + 0xFF00,
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memory_.begin() + (0xFF << 16) + 0xFFFF + 1, 0);
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// Copy data into rom_ vector
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rom_.resize(kROMSize);
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std::copy(memory_.begin() + kROMStart,
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memory_.begin() + kROMStart + kROMSize, rom_.begin());
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// Copy data into ram_ vector
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ram_.resize(kRAMSize);
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std::copy(memory_.begin() + kRAMStart,
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memory_.begin() + kRAMStart + kRAMSize, ram_.begin());
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// Copy data into vram_ vector
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vram_.resize(kVRAMSize);
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std::copy(memory_.begin() + kVRAMStart,
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memory_.begin() + kVRAMStart + kVRAMSize, vram_.begin());
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// Copy data into oam_ vector
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oam_.resize(kOAMSize);
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std::copy(memory_.begin() + kOAMStart,
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memory_.begin() + kOAMStart + kOAMSize, oam_.begin());
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return offset;
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}
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memory::RomInfo ReadRomHeader();
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uint8_t cart_read(uint8_t bank, uint16_t adr);
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void cart_write(uint8_t bank, uint16_t adr, uint8_t val);
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uint8_t cart_readLorom(uint8_t bank, uint16_t adr);
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void cart_writeLorom(uint8_t bank, uint16_t adr, uint8_t val);
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uint8_t cart_readHirom(uint8_t bank, uint16_t adr);
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uint8_t cart_readExHirom(uint8_t bank, uint16_t adr);
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void cart_writeHirom(uint8_t bank, uint16_t adr, uint8_t val);
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uint8_t ReadByte(uint32_t address) const override {
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uint32_t mapped_address = GetMappedAddress(address);
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NotifyObservers(mapped_address, /*data=*/0);
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return memory_.at(mapped_address);
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}
|
||||
uint16_t ReadWord(uint32_t address) const override {
|
||||
uint32_t mapped_address = GetMappedAddress(address);
|
||||
NotifyObservers(mapped_address, /*data=*/0);
|
||||
return static_cast<uint16_t>(memory_.at(mapped_address)) |
|
||||
(static_cast<uint16_t>(memory_.at(mapped_address + 1)) << 8);
|
||||
}
|
||||
uint32_t ReadWordLong(uint32_t address) const override {
|
||||
uint32_t mapped_address = GetMappedAddress(address);
|
||||
NotifyObservers(mapped_address, /*data=*/0);
|
||||
return static_cast<uint32_t>(memory_.at(mapped_address)) |
|
||||
(static_cast<uint32_t>(memory_.at(mapped_address + 1)) << 8) |
|
||||
(static_cast<uint32_t>(memory_.at(mapped_address + 2)) << 16);
|
||||
@@ -276,7 +221,6 @@ class MemoryImpl : public Memory, public Loggable {
|
||||
std::vector<uint8_t> ReadByteVector(uint32_t address,
|
||||
uint16_t length) const override {
|
||||
uint32_t mapped_address = GetMappedAddress(address);
|
||||
NotifyObservers(mapped_address, /*data=*/0);
|
||||
return std::vector<uint8_t>(memory_.begin() + mapped_address,
|
||||
memory_.begin() + mapped_address + length);
|
||||
}
|
||||
@@ -343,8 +287,6 @@ class MemoryImpl : public Memory, public Loggable {
|
||||
(static_cast<uint32_t>(mid) << 8) | low;
|
||||
}
|
||||
|
||||
void AddObserver(Observer* observer) { observers_.push_back(observer); }
|
||||
|
||||
// Stack Pointer access.
|
||||
uint16_t SP() const override { return SP_; }
|
||||
void SetSP(uint16_t value) override { SP_ = value; }
|
||||
@@ -363,61 +305,69 @@ class MemoryImpl : public Memory, public Loggable {
|
||||
auto begin() const { return memory_.begin(); }
|
||||
auto end() const { return memory_.end(); }
|
||||
auto data() const { return memory_.data(); }
|
||||
void set_open_bus(uint8_t value) override { open_bus_ = value; }
|
||||
auto open_bus() const -> uint8_t override { return open_bus_; }
|
||||
auto hdma_init_requested() const -> bool override {
|
||||
return hdma_init_requested_;
|
||||
}
|
||||
auto hdma_run_requested() const -> bool override {
|
||||
return hdma_run_requested_;
|
||||
}
|
||||
void init_hdma_request() override { hdma_init_requested_ = true; }
|
||||
void run_hdma_request() override { hdma_run_requested_ = true; }
|
||||
void set_hdma_run_requested(bool value) override {
|
||||
hdma_run_requested_ = value;
|
||||
}
|
||||
void set_hdma_init_requested(bool value) override {
|
||||
hdma_init_requested_ = value;
|
||||
}
|
||||
void set_pal_timing(bool value) override { pal_timing_ = value; }
|
||||
void set_h_pos(uint16_t value) override { h_pos_ = value; }
|
||||
void set_v_pos(uint16_t value) override { v_pos_ = value; }
|
||||
auto h_pos() const -> uint16_t override { return h_pos_; }
|
||||
auto v_pos() const -> uint16_t override { return v_pos_; }
|
||||
auto pal_timing() const -> bool override { return pal_timing_; }
|
||||
|
||||
auto dma_state() -> uint8_t& { return dma_state_; }
|
||||
void set_dma_state(uint8_t value) { dma_state_ = value; }
|
||||
auto dma_channels() -> DmaChannel* { return channel; }
|
||||
|
||||
// Define memory regions
|
||||
std::vector<uint8_t> rom_;
|
||||
std::vector<uint8_t> ram_;
|
||||
std::vector<uint8_t> vram_;
|
||||
std::vector<uint8_t> oam_;
|
||||
|
||||
private:
|
||||
uint32_t GetMappedAddress(uint32_t address) const {
|
||||
uint8_t bank = address >> 16;
|
||||
uint32_t offset = address & 0xFFFF;
|
||||
|
||||
if (mapping_ == MemoryMapping::PC_ADDRESS) {
|
||||
return address;
|
||||
}
|
||||
|
||||
if (bank <= 0x3F) {
|
||||
if (address <= 0x1FFF) {
|
||||
return (0x7E << 16) + offset; // Shadow RAM
|
||||
} else if (address <= 0x5FFF) {
|
||||
return (bank << 16) + (offset - 0x2000) + 0x2000; // Hardware Registers
|
||||
} else if (address <= 0x7FFF) {
|
||||
return offset - 0x6000 + 0x6000; // Expansion RAM
|
||||
} else {
|
||||
// Return lorom mapping
|
||||
return (bank << 16) + (offset - 0x8000) + 0x8000; // ROM
|
||||
}
|
||||
} else if (bank == 0x7D) {
|
||||
return offset + 0x7D0000; // SRAM
|
||||
} else if (bank == 0x7E || bank == 0x7F) {
|
||||
return offset + 0x7E0000; // System RAM
|
||||
} else if (bank >= 0x80) {
|
||||
// Handle HiROM and mirrored areas
|
||||
}
|
||||
|
||||
return address; // Return the original address if no mapping is defined
|
||||
}
|
||||
|
||||
void NotifyObservers(uint32_t address, uint16_t data) const {
|
||||
for (auto observer : observers_) {
|
||||
observer->Notify(address, data);
|
||||
}
|
||||
}
|
||||
uint32_t GetMappedAddress(uint32_t address) const;
|
||||
|
||||
bool verbose_ = false;
|
||||
|
||||
std::vector<Observer*> observers_;
|
||||
// DMA requests
|
||||
bool hdma_run_requested_ = false;
|
||||
bool hdma_init_requested_ = false;
|
||||
|
||||
// Memory (64KB)
|
||||
std::vector<uint8_t> memory_;
|
||||
bool pal_timing_ = false;
|
||||
|
||||
// Frame timing
|
||||
uint16_t h_pos_ = 0;
|
||||
uint16_t v_pos_ = 0;
|
||||
|
||||
// Dma State
|
||||
uint8_t dma_state_ = 0;
|
||||
|
||||
// Dma Channels
|
||||
DmaChannel channel[8];
|
||||
|
||||
// Open bus
|
||||
uint8_t open_bus_ = 0;
|
||||
|
||||
// Stack Pointer
|
||||
uint16_t SP_ = 0x01FF;
|
||||
|
||||
MemoryMapping mapping_ = MemoryMapping::SNES_LOROM;
|
||||
// Cart Type
|
||||
uint8_t type_;
|
||||
|
||||
// Memory (64KB)
|
||||
std::vector<uint8_t> memory_;
|
||||
};
|
||||
|
||||
void DrawSnesMemoryMapping(const MemoryImpl& memory);
|
||||
|
||||
@@ -72,6 +72,21 @@ class MockMemory : public Memory {
|
||||
MOCK_CONST_METHOD1(at, uint8_t(int i));
|
||||
uint8_t operator[](int i) const override { return memory_[i]; }
|
||||
|
||||
MOCK_METHOD0(init_hdma_request, void());
|
||||
MOCK_METHOD0(run_hdma_request, void());
|
||||
MOCK_METHOD1(set_hdma_run_requested, void(bool value));
|
||||
MOCK_METHOD1(set_hdma_init_requested, void(bool value));
|
||||
MOCK_CONST_METHOD0(hdma_init_requested, bool());
|
||||
MOCK_CONST_METHOD0(hdma_run_requested, bool());
|
||||
MOCK_METHOD1(set_pal_timing, void(bool value));
|
||||
MOCK_CONST_METHOD0(pal_timing, bool());
|
||||
MOCK_CONST_METHOD0(h_pos, uint16_t());
|
||||
MOCK_CONST_METHOD0(v_pos, uint16_t());
|
||||
MOCK_METHOD1(set_h_pos, void(uint16_t value));
|
||||
MOCK_METHOD1(set_v_pos, void(uint16_t value));
|
||||
MOCK_METHOD1(set_open_bus, void(uint8_t value));
|
||||
MOCK_CONST_METHOD0(open_bus, uint8_t());
|
||||
|
||||
void SetMemoryContents(const std::vector<uint8_t>& data) {
|
||||
if (data.size() > memory_.size()) {
|
||||
memory_.resize(data.size());
|
||||
|
||||
Reference in New Issue
Block a user