Add DmaChannel, implement DMA functions
This commit is contained in:
scawful
@@ -6,72 +6,340 @@ namespace yaze {
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namespace app {
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namespace emu {
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namespace memory {
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namespace dma {
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void DirectMemoryAccess::StartDMATransfer(uint8_t channelMask) {
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for (int i = 0; i < 8; ++i) {
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if ((channelMask & (1 << i)) != 0) {
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Channel& ch = channels[i];
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static const int bAdrOffsets[8][4] = {{0, 0, 0, 0}, {0, 1, 0, 1}, {0, 0, 0, 0},
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{0, 0, 1, 1}, {0, 1, 2, 3}, {0, 1, 0, 1},
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{0, 0, 0, 0}, {0, 0, 1, 1}};
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// Validate channel parameters (e.g., DMAPn, BBADn, A1Tn, DASn)
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// ...
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static const int transferLength[8] = {1, 2, 2, 4, 4, 4, 2, 4};
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// Determine the transfer direction based on the DMAPn register
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bool fromMemory = (ch.DMAPn & 0x80) != 0;
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uint8_t Read(MemoryImpl* memory, uint16_t adr) {
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auto channel = memory->dma_channels();
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uint8_t c = (adr & 0x70) >> 4;
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switch (adr & 0xf) {
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case 0x0: {
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uint8_t val = channel[c].mode;
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val |= channel[c].fixed << 3;
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val |= channel[c].decrement << 4;
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val |= channel[c].unusedBit << 5;
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val |= channel[c].indirect << 6;
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val |= channel[c].fromB << 7;
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return val;
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}
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case 0x1: {
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return channel[c].bAdr;
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}
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case 0x2: {
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return channel[c].aAdr & 0xff;
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}
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case 0x3: {
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return channel[c].aAdr >> 8;
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}
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case 0x4: {
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return channel[c].aBank;
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}
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case 0x5: {
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return channel[c].size & 0xff;
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}
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case 0x6: {
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return channel[c].size >> 8;
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}
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case 0x7: {
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return channel[c].indBank;
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}
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case 0x8: {
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return channel[c].tableAdr & 0xff;
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}
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case 0x9: {
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return channel[c].tableAdr >> 8;
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}
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case 0xa: {
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return channel[c].repCount;
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}
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case 0xb:
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case 0xf: {
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return channel[c].unusedByte;
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}
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default: {
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return memory->open_bus();
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}
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}
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}
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// Determine the transfer size based on the DMAPn register
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bool transferTwoBytes = (ch.DMAPn & 0x40) != 0;
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void Write(MemoryImpl* memory, uint16_t adr, uint8_t val) {
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auto channel = memory->dma_channels();
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uint8_t c = (adr & 0x70) >> 4;
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switch (adr & 0xf) {
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case 0x0: {
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channel[c].mode = val & 0x7;
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channel[c].fixed = val & 0x8;
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channel[c].decrement = val & 0x10;
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channel[c].unusedBit = val & 0x20;
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channel[c].indirect = val & 0x40;
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channel[c].fromB = val & 0x80;
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break;
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}
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case 0x1: {
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channel[c].bAdr = val;
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break;
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}
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case 0x2: {
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channel[c].aAdr = (channel[c].aAdr & 0xff00) | val;
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break;
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}
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case 0x3: {
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channel[c].aAdr = (channel[c].aAdr & 0xff) | (val << 8);
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break;
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}
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case 0x4: {
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channel[c].aBank = val;
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break;
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}
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case 0x5: {
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channel[c].size = (channel[c].size & 0xff00) | val;
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break;
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}
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case 0x6: {
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channel[c].size = (channel[c].size & 0xff) | (val << 8);
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break;
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}
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case 0x7: {
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channel[c].indBank = val;
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break;
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}
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case 0x8: {
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channel[c].tableAdr = (channel[c].tableAdr & 0xff00) | val;
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break;
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}
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case 0x9: {
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channel[c].tableAdr = (channel[c].tableAdr & 0xff) | (val << 8);
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break;
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}
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case 0xa: {
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channel[c].repCount = val;
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break;
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}
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case 0xb:
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case 0xf: {
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channel[c].unusedByte = val;
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break;
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}
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default: {
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break;
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}
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}
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}
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// Perform the DirectMemoryAccess transfer based on the channel parameters
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std::cout << "Starting DirectMemoryAccess transfer for channel " << i
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<< std::endl;
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void DoDma(SNES* snes, MemoryImpl* memory, int cpuCycles) {
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auto channel = memory->dma_channels();
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for (uint16_t j = 0; j < ch.DASn; ++j) {
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// Read a byte or two bytes from memory based on the transfer size
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// ...
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// align to multiple of 8
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snes->SyncCycles(true, 8);
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// Write the data to the B-bus address (BBADn) if transferring from
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// memory
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// ...
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// full transfer overhead
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WaitCycle(snes, memory);
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for (int i = 0; i < 8; i++) {
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if (!channel[i].dmaActive) continue;
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// do channel i
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WaitCycle(snes, memory); // overhead per channel
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int offIndex = 0;
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while (channel[i].dmaActive) {
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WaitCycle(snes, memory);
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TransferByte(snes, memory, channel[i].aAdr, channel[i].aBank,
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channel[i].bAdr + bAdrOffsets[channel[i].mode][offIndex++],
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channel[i].fromB);
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offIndex &= 3;
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if (!channel[i].fixed) {
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channel[i].aAdr += channel[i].decrement ? -1 : 1;
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}
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channel[i].size--;
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if (channel[i].size == 0) {
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channel[i].dmaActive = false;
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}
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}
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}
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// Update the A1Tn register based on the transfer direction
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if (fromMemory) {
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ch.A1Tn += transferTwoBytes ? 2 : 1;
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} else {
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ch.A1Tn -= transferTwoBytes ? 2 : 1;
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// re-align to cpu cycles
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snes->SyncCycles(false, cpuCycles);
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}
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void HandleDma(SNES* snes, MemoryImpl* memory, int cpu_cycles) {
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// if hdma triggered, do it, except if dmastate indicates dma will be done now
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// (it will be done as part of the dma in that case)
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if (memory->hdma_init_requested() && memory->dma_state() != 2)
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InitHdma(snes, memory, true, cpu_cycles);
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if (memory->hdma_run_requested() && memory->dma_state() != 2)
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DoHdma(snes, memory, true, cpu_cycles);
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if (memory->dma_state() == 1) {
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memory->set_dma_state(2);
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return;
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}
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if (memory->dma_state() == 2) {
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// do dma
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DoDma(snes, memory, cpu_cycles);
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memory->set_dma_state(0);
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}
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}
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void WaitCycle(SNES* snes, MemoryImpl* memory) {
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// run hdma if requested, no sync (already sycned due to dma)
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if (memory->hdma_init_requested()) InitHdma(snes, memory, false, 0);
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if (memory->hdma_run_requested()) DoHdma(snes, memory, false, 0);
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snes->RunCycles(8);
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}
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void InitHdma(SNES* snes, MemoryImpl* memory, bool do_sync, int cpu_cycles) {
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auto channel = memory->dma_channels();
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memory->set_hdma_init_requested(false);
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bool hdmaEnabled = false;
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// check if a channel is enabled, and do reset
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for (int i = 0; i < 8; i++) {
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if (channel[i].hdmaActive) hdmaEnabled = true;
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channel[i].doTransfer = false;
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channel[i].terminated = false;
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}
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if (!hdmaEnabled) return;
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if (do_sync) snes->SyncCycles(true, 8);
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// full transfer overhead
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snes->RunCycles(8);
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for (int i = 0; i < 8; i++) {
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if (channel[i].hdmaActive) {
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// terminate any dma
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channel[i].dmaActive = false;
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// load address, repCount, and indirect address if needed
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snes->RunCycles(8);
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channel[i].tableAdr = channel[i].aAdr;
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channel[i].repCount =
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snes->Read((channel[i].aBank << 16) | channel[i].tableAdr++);
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if (channel[i].repCount == 0) channel[i].terminated = true;
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if (channel[i].indirect) {
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snes->RunCycles(8);
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channel[i].size =
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snes->Read((channel[i].aBank << 16) | channel[i].tableAdr++);
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snes->RunCycles(8);
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channel[i].size |=
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snes->Read((channel[i].aBank << 16) | channel[i].tableAdr++) << 8;
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}
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channel[i].doTransfer = true;
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}
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}
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if (do_sync) snes->SyncCycles(false, cpu_cycles);
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}
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void DoHdma(SNES* snes, MemoryImpl* memory, bool do_sync, int cycles) {
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auto channel = memory->dma_channels();
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memory->set_hdma_run_requested(false);
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bool hdmaActive = false;
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int lastActive = 0;
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for (int i = 0; i < 8; i++) {
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if (channel[i].hdmaActive) {
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hdmaActive = true;
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if (!channel[i].terminated) lastActive = i;
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}
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}
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if (!hdmaActive) return;
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if (do_sync) snes->SyncCycles(true, 8);
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// full transfer overhead
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snes->RunCycles(8);
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// do all copies
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for (int i = 0; i < 8; i++) {
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// terminate any dma
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if (channel[i].hdmaActive) channel[i].dmaActive = false;
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if (channel[i].hdmaActive && !channel[i].terminated) {
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// do the hdma
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if (channel[i].doTransfer) {
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for (int j = 0; j < transferLength[channel[i].mode]; j++) {
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snes->RunCycles(8);
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if (channel[i].indirect) {
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TransferByte(snes, memory, channel[i].size++, channel[i].indBank,
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channel[i].bAdr + bAdrOffsets[channel[i].mode][j],
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channel[i].fromB);
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} else {
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TransferByte(snes, memory, channel[i].tableAdr++, channel[i].aBank,
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channel[i].bAdr + bAdrOffsets[channel[i].mode][j],
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channel[i].fromB);
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}
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}
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}
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// Update the channel registers after the transfer (e.g., A1Tn, DASn)
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// ...
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}
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}
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MDMAEN = channelMask; // Set the MDMAEN register to the channel mask
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}
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void DirectMemoryAccess::EnableHDMATransfers(uint8_t channelMask) {
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for (int i = 0; i < 8; ++i) {
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if ((channelMask & (1 << i)) != 0) {
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Channel& ch = channels[i];
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// Validate channel parameters (e.g., DMAPn, BBADn, A1Tn, A2An, NLTRn)
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// ...
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// Perform the HDMA setup based on the channel parameters
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std::cout << "Enabling HDMA transfer for channel " << i << std::endl;
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// Read the HDMA table from memory starting at A1Tn
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// ...
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// Update the A2An register based on the HDMA table
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// ...
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// Update the NLTRn register based on the HDMA table
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// ...
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// do all updates
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for (int i = 0; i < 8; i++) {
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if (channel[i].hdmaActive && !channel[i].terminated) {
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channel[i].repCount--;
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channel[i].doTransfer = channel[i].repCount & 0x80;
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snes->RunCycles(8);
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uint8_t newRepCount =
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snes->Read((channel[i].aBank << 16) | channel[i].tableAdr);
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if ((channel[i].repCount & 0x7f) == 0) {
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channel[i].repCount = newRepCount;
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channel[i].tableAdr++;
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if (channel[i].indirect) {
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if (channel[i].repCount == 0 && i == lastActive) {
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// if this is the last active channel, only fetch high, and use 0
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// for low
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channel[i].size = 0;
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} else {
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snes->RunCycles(8);
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channel[i].size =
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snes->Read((channel[i].aBank << 16) | channel[i].tableAdr++);
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}
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snes->RunCycles(8);
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channel[i].size |=
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snes->Read((channel[i].aBank << 16) | channel[i].tableAdr++) << 8;
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}
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if (channel[i].repCount == 0) channel[i].terminated = true;
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channel[i].doTransfer = true;
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}
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}
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}
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HDMAEN = channelMask; // Set the HDMAEN register to the channel mask
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if (do_sync) snes->SyncCycles(false, cycles);
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}
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void TransferByte(SNES* snes, MemoryImpl* memory, uint16_t aAdr, uint8_t aBank,
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uint8_t bAdr, bool fromB) {
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// accessing 0x2180 via b-bus while a-bus accesses ram gives open bus
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bool validB =
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!(bAdr == 0x80 &&
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(aBank == 0x7e || aBank == 0x7f ||
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((aBank < 0x40 || (aBank >= 0x80 && aBank < 0xc0)) && aAdr < 0x2000)));
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// accesing b-bus, or dma regs via a-bus gives open bus
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bool validA = !((aBank < 0x40 || (aBank >= 0x80 && aBank < 0xc0)) &&
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(aAdr == 0x420b || aAdr == 0x420c ||
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(aAdr >= 0x4300 && aAdr < 0x4380) ||
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(aAdr >= 0x2100 && aAdr < 0x2200)));
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if (fromB) {
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uint8_t val = validB ? snes->ReadBBus(bAdr) : memory->open_bus();
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if (validA) snes->Write((aBank << 16) | aAdr, val);
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} else {
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uint8_t val =
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validA ? snes->Read((aBank << 16) | aAdr) : memory->open_bus();
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if (validB) snes->WriteBBus(bAdr, val);
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}
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}
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void StartDma(MemoryImpl* memory, uint8_t val, bool hdma) {
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auto channel = memory->dma_channels();
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for (int i = 0; i < 8; i++) {
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if (hdma) {
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channel[i].hdmaActive = val & (1 << i);
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} else {
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channel[i].dmaActive = val & (1 << i);
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}
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}
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if (!hdma) {
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memory->set_dma_state(val != 0 ? 1 : 0);
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}
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}
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} // namespace dma
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} // namespace memory
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} // namespace emu
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} // namespace app
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@@ -3,56 +3,31 @@
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#include <cstdint>
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#include "app/emu/memory/memory.h"
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#include "app/emu/snes.h"
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namespace yaze {
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namespace app {
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namespace emu {
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namespace memory {
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namespace dma {
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class DirectMemoryAccess {
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public:
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DirectMemoryAccess() {
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// Initialize DMA and HDMA channels
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for (int i = 0; i < 8; ++i) {
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channels[i].DMAPn = 0;
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channels[i].BBADn = 0;
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channels[i].UNUSEDn = 0;
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channels[i].A1Tn = 0xFFFFFF;
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channels[i].DASn = 0xFFFF;
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channels[i].A2An = 0xFFFF;
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channels[i].NLTRn = 0xFF;
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}
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}
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void HandleDma(SNES* snes, MemoryImpl* memory, int cpu_cycles);
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// DMA Transfer Modes
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enum class DMA_TRANSFER_TYPE {
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OAM,
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PPUDATA,
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CGDATA,
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FILL_VRAM,
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CLEAR_VRAM,
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RESET_VRAM
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};
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void WaitCycle(SNES* snes, MemoryImpl* memory);
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// Functions for handling DMA and HDMA transfers
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void StartDMATransfer(uint8_t channels);
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void EnableHDMATransfers(uint8_t channels);
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void InitHdma(SNES* snes, MemoryImpl* memory, bool do_sync, int cycles);
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void DoHdma(SNES* snes, MemoryImpl* memory, bool do_sync, int cycles);
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// Structure for DMA and HDMA channel registers
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struct Channel {
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uint8_t DMAPn; // DMA/HDMA parameters
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uint8_t BBADn; // B-bus address
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uint8_t UNUSEDn; // Unused byte
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uint32_t A1Tn; // DMA Current Address / HDMA Table Start Address
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uint16_t DASn; // DMA Byte-Counter / HDMA indirect table address
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uint16_t A2An; // HDMA Table Current Address
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uint8_t NLTRn; // HDMA Line-Counter
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};
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Channel channels[8];
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void TransferByte(SNES* snes, MemoryImpl* memory, uint16_t aAdr, uint8_t aBank,
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uint8_t bAdr, bool fromB);
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uint8_t MDMAEN = 0; // Start DMA transfer
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uint8_t HDMAEN = 0; // Enable HDMA transfers
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};
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uint8_t Read(MemoryImpl* memory, uint16_t address);
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void Write(MemoryImpl* memory, uint16_t address, uint8_t data);
|
||||
void StartDma(MemoryImpl* memory, uint8_t val, bool hdma);
|
||||
void DoDma(MemoryImpl* memory, int cycles);
|
||||
|
||||
} // namespace dma
|
||||
} // namespace memory
|
||||
} // namespace emu
|
||||
} // namespace app
|
||||
|
||||
37
src/app/emu/memory/dma_channel.h
Normal file
37
src/app/emu/memory/dma_channel.h
Normal file
@@ -0,0 +1,37 @@
|
||||
#ifndef YAZE_APP_EMU_MEMORY_DMA_CHANNEL_H
|
||||
#define YAZE_APP_EMU_MEMORY_DMA_CHANNEL_H
|
||||
|
||||
#include <cstdint>
|
||||
|
||||
namespace yaze {
|
||||
namespace app {
|
||||
namespace emu {
|
||||
namespace memory {
|
||||
|
||||
typedef struct DmaChannel {
|
||||
uint8_t bAdr;
|
||||
uint16_t aAdr;
|
||||
uint8_t aBank;
|
||||
uint16_t size; // also indirect hdma adr
|
||||
uint8_t indBank; // hdma
|
||||
uint16_t tableAdr; // hdma
|
||||
uint8_t repCount; // hdma
|
||||
uint8_t unusedByte;
|
||||
bool dmaActive;
|
||||
bool hdmaActive;
|
||||
uint8_t mode;
|
||||
bool fixed;
|
||||
bool decrement;
|
||||
bool indirect; // hdma
|
||||
bool fromB;
|
||||
bool unusedBit;
|
||||
bool doTransfer; // hdma
|
||||
bool terminated; // hdma
|
||||
} DmaChannel;
|
||||
|
||||
} // namespace memory
|
||||
} // namespace emu
|
||||
} // namespace app
|
||||
} // namespace yaze
|
||||
|
||||
#endif // YAZE_APP_EMU_MEMORY_DMA_CHANNEL_H
|
||||
Reference in New Issue
Block a user