Apu callback, CPU instruction lengths
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@@ -43,11 +43,14 @@ void APU::Update() {
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for (auto i = 0; i < cycles_to_run; ++i) {
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for (auto i = 0; i < cycles_to_run; ++i) {
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// Update the APU
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// Update the APU
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// ...
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UpdateChannelSettings();
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// Update the SPC700
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// Update the SPC700
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// ...
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uint8_t opcode = spc700_.read(spc700_.PC);
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spc700_.ExecuteInstructions(opcode);
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}
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}
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ProcessSamples();
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}
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}
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void APU::ProcessSamples() {
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void APU::ProcessSamples() {
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@@ -157,6 +157,10 @@ class APU : public Observer {
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}
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}
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}
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}
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void SetReadyCallback(std::function<void()> callback) {
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ready_callback_ = callback;
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}
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private:
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private:
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// Constants for communication
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// Constants for communication
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static const uint8_t READY_SIGNAL_0 = 0xAA;
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static const uint8_t READY_SIGNAL_0 = 0xAA;
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@@ -187,6 +191,8 @@ class APU : public Observer {
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DigitalSignalProcessor dsp_;
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DigitalSignalProcessor dsp_;
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SPC700 spc700_{aram_};
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SPC700 spc700_{aram_};
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std::vector<int16_t> audioSamples_;
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std::vector<int16_t> audioSamples_;
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std::function<void()> ready_callback_;
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};
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};
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} // namespace emu
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} // namespace emu
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@@ -368,14 +368,14 @@ void CPU::ExecuteInstruction(uint8_t opcode) {
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case 0xD0: // BNE Branch if not equal (zero clear)
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case 0xD0: // BNE Branch if not equal (zero clear)
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{
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{
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operand = FetchByte();
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operand = FetchSignedByte();
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BNE(operand);
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BNE(operand);
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break;
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break;
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}
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}
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case 0x10: // BPL Branch if plus (negative clear)
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case 0x10: // BPL Branch if plus (negative clear)
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{
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{
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operand = FetchByte();
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operand = FetchSignedByte();
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BPL(operand);
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BPL(operand);
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break;
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break;
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}
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}
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@@ -390,6 +390,18 @@ void CPU::ExecuteInstruction(uint8_t opcode) {
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case 0x00: // BRK Break
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case 0x00: // BRK Break
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{
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{
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BRK();
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BRK();
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std::cout << "BRK" << std::endl;
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// Print all the registers
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std::cout << "A: " << std::hex << std::setw(2) << std::setfill('0') << (int)A << std::endl;
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std::cout << "X: " << std::hex << std::setw(2) << std::setfill('0') << (int)X << std::endl;
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std::cout << "Y: " << std::hex << std::setw(2) << std::setfill('0') << (int)Y << std::endl;
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std::cout << "S: " << std::hex << std::setw(2) << std::setfill('0') << (int)SP() << std::endl;
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std::cout << "PC: " << std::hex << std::setw(4) << std::setfill('0') << (int)PC << std::endl;
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std::cout << "PB: " << std::hex << std::setw(2) << std::setfill('0') << (int)PB << std::endl;
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std::cout << "D: " << std::hex << std::setw(4) << std::setfill('0') << (int)D << std::endl;
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std::cout << "DB: " << std::hex << std::setw(2) << std::setfill('0') << (int)DB << std::endl;
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std::cout << "E: " << std::hex << std::setw(2) << std::setfill('0') << (int)E << std::endl;
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break;
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break;
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}
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}
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@@ -1730,6 +1742,13 @@ uint8_t CPU::GetInstructionLength(uint8_t opcode) {
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case 0x93: // STA SR Indirect Indexed, Y
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case 0x93: // STA SR Indirect Indexed, Y
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case 0x95: // STA Direct Page Indexed, X
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case 0x95: // STA Direct Page Indexed, X
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case 0x96: // STX Direct Page Indexed, Y
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case 0x96: // STX Direct Page Indexed, Y
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case 0xC7: // CMP Direct Page Indirect Long
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case 0xD7: // CMP DP Indirect Long Indexed, Y
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case 0xD2: // CMP DP Indirect
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case 0xD1: // CMP DP Indirect Indexed, Y
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case 0x03: // ORA Stack Relative
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case 0x13: // ORA SR Indirect Indexed, Y
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case 0x07: // ORA Direct Page Indirect Long
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return 2;
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return 2;
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case 0x69: // ADC Immediate
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case 0x69: // ADC Immediate
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@@ -1772,6 +1791,11 @@ uint8_t CPU::GetInstructionLength(uint8_t opcode) {
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case 0x5D: // EOR Absolute Indexed, X
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case 0x5D: // EOR Absolute Indexed, X
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case 0x59: // EOR Absolute Indexed, Y
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case 0x59: // EOR Absolute Indexed, Y
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case 0x83: // STA Stack Relative Indirect Indexed, Y
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case 0x83: // STA Stack Relative Indirect Indexed, Y
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case 0xCE: // DEC Absolute
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case 0xD5: // CMP DP Indexed, X
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case 0xD9: // CMP Absolute Indexed, Y
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case 0xDD: // CMP Absolute Indexed, X
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case 0x0C: // TSB Absolute
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return 3;
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return 3;
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case 0x2F: // AND Absolute Long
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case 0x2F: // AND Absolute Long
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