274 lines
10 KiB
NASM
274 lines
10 KiB
NASM
; ==============================================================================
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; SNES Hardware Registers
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; ==============================================================================
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; Shorthand legend:
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; Addr = Address
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; APU = Audio Processing Unit
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; BG = BackGround
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; CGRAM = Color Generator RAM
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; Des = Designation
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; H = Horizontal
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; HDMA = Horizontal Direct Memory Access
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; HV = H/V or Horizontal/Vertical
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; Init = Initial
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; IO = I/O or Input/Output
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; IRQ = Interupt ReQuest
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; NMI = Non-Maskable Interupt
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; Num = Number
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; MULT = Multiply/Multiplication
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; OAM = Object Attribute Memory
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; OBJ = Object
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; Pos = Position
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; PPU = Picture Processing Unit
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; V = Vertical
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; Val = Value
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; VRAM = Video RAM
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; Names taken from:
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; https://en.wikibooks.org/wiki/Super_NES_Programming/SNES_Hardware_Registers
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; Further details on each register can be found here:
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; https://github.com/gilligan/snesdev/blob/master/docs/snes_registers.txt
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; https://www.youtube.com/watch?v=-4OOuRvTXrM&t=167s
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org $7E2100 ; Remove for asar 2.0.
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struct SNES $7E2100
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{
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.ScreenDisplay: skip $01 ; $2100
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.OAMSizeAndDataDes: skip $01 ; $2101
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.OAMAccessAddr: skip $02 ; $2102
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.OMADataWrite: skip $01 ; $2104
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.BGModeAndTileSize: skip $01 ; $2105
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.MosaicAndBGEnable: skip $01 ; $2106
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.BG1AddrAndSize: skip $01 ; $2107
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.BG2AddrAndSize: skip $01 ; $2108
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.BG3AddrAndSize: skip $01 ; $2109
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.BG4AddrAndSize: skip $01 ; $210A
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.BG1And2TileDataDes: skip $01 ; $210B
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.BG3And4TileDataDes: skip $01 ; $210C
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.BG1HScrollOffset: skip $01 ; $210D
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.BG1VScrollOffset: skip $01 ; $210E
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.BG2HScrollOffset: skip $01 ; $210F
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.BG2VScrollOffset: skip $01 ; $2110
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.BG3HScrollOffset: skip $01 ; $2111
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.BG3VScrollOffset: skip $01 ; $2112
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.BG4HScrollOffset: skip $01 ; $2113
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.BG4VScrollOffset: skip $01 ; $2114
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.VRAMAddrIncrementVal: skip $01 ; $2115
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.VRAMAddrReadWriteLow: skip $01 ; $2116
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.VRAMAddrReadWriteHigh: skip $01 ; $2117
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.VRAMDataWriteLow: skip $01 ; $2118
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.VRAMDataWriteHigh: skip $01 ; $2119
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.Mode7Init skip $01 ; $211A
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.Mode7MatrixA skip $01 ; $211B
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.Mode7MatrixB skip $01 ; $211C
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.Mode7MatrixC skip $01 ; $211D
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.Mode7MatrixD skip $01 ; $211E
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.Mode7CenterPosX skip $01 ; $211F
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.Mode7CenterPosY skip $01 ; $2120
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.CGRAMWriteAddr skip $01 ; $2121
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.CGRAMWriteData skip $01 ; $2122
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.BG1And2WindowMask skip $01 ; $2123
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.BG3And4WindowMask skip $01 ; $2124
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.OBJAndColorWindow skip $01 ; $2125
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.Window1LeftPosDes skip $01 ; $2126
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.Window1RightPosDes skip $01 ; $2127
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.Window2LeftPosDes skip $01 ; $2128
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.Window2RightPosDes skip $01 ; $2129
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.BG123And4WindowLogic skip $01 ; $212A
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.ColorAndOBJWindowLogic skip $01 ; $212B
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.BGAndOBJEnableMainScreen skip $01 ; $212C
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.BGAndOBJEnableSubScreen skip $01 ; $212D
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.WindowMaskDesMainScreen skip $01 ; $212E
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.WindowMaskDesSubScreen skip $01 ; $212F
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.InitColorAddition skip $01 ; $2130
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.AddSubtractSelectAndEnable skip $01 ; $2131
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.FixedColorData skip $01 ; $2132
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.ScreenInit skip $01 ; $2133
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.MultResultLow skip $01 ; $2134
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.MultResultMid skip $01 ; $2135
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.MultResultHigh skip $01 ; $2136
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.HVCounterSoftwareLatch skip $01 ; $2137
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.OAMReadDataLowHigh skip $01 ; $2138
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.VRAMReadDataLow skip $01 ; $2139
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.VRAMReadDataHigh skip $01 ; $213A
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.CGRAMReadDataLowHigh skip $01 ; $213B
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.HCounterData skip $01 ; $213C
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.VCounterData skip $01 ; $213D
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.PPUStatusFlag1 skip $01 ; $213E
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.PPUStatusFlag2 skip $01 ; $213F
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.APUIOPort0 skip $01 ; $2140
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.APUIOPort1 skip $01 ; $2141
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.APUIOPort2 skip $01 ; $2142
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.APUIOPort3 skip $01 ; $2143
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base $2180
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.IndirectWorkRAMPort: skip $01 ; $2180
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.IndirectWorkRAMAddrLow: skip $01 ; $2181
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.IndirectWorkRAMAddrMid: skip $01 ; $2182
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.IndirectWorkRAMAddrHigh: skip $01 ; $2183
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base $4200
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.NMIVHCountJoypadEnable: skip $01 ; $4200
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.ProgrammableIOPortOut: skip $01 ; $4201
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.MultiplicandA: skip $01 ; $4202
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.MultiplierB: skip $01 ; $4203
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.DividendLow: skip $01 ; $4204
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.DividendHigh: skip $01 ; $4205
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.DivisorB: skip $01 ; $4206
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.HCountTimer: skip $01 ; $4207
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.HCountTimerHigh: skip $01 ; $4208
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.VCountTImer: skip $01 ; $4209
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.VCountTimerHigh: skip $01 ; $420A
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.DMAChannelEnable: skip $01 ; $420B
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.HDMAChannelEnable: skip $01 ; $420C
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.CycleSpeedDes: skip $01 ; $420D
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base $4210
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.NMIFlagAndCPUVersionNum: skip $01 ; $4210
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.IRQFlagByHVCountTimer: skip $01 ; $4211
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.HVBlankFlagsAndJoyStatus: skip $01 ; $4212
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.ProgrammableIOPortIn: skip $01 ; $4213
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.DivideResultQuotientLow: skip $01 ; $4214
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.DivideResultQuotientHigh: skip $01 ; $4215
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.RemainderResultLow: skip $01 ; $4216
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.RemainderResultHigh: skip $01 ; $4217
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.JoyPad1DataLow: skip $01 ; $4218
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.JoyPad1DataHigh: skip $01 ; $4219
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.JoyPad2DataLow: skip $01 ; $421A
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.JoyPad2DataHigh: skip $01 ; $421B
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.JoyPad3DataLow: skip $01 ; $421C
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.JoyPad3DataHigh: skip $01 ; $421D
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.JoyPad4DataLow: skip $01 ; $421E
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.JoyPad4DataHigh: skip $01 ; $421F
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}
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endstruct
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struct DMA $7E4300
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{
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; Channel 0
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.0_TransferParameters: skip $01 ; $4300
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.0_DestinationAddr: skip $01 ; $4301
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.0_SourceAddrOffsetLow: skip $01 ; $4302
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.0_SourceAddrOffsetHigh: skip $01 ; $4303
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.0_SourceAddrBank: skip $01 ; $4304
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.0_TransferSizeLow: skip $01 ; $4305
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.0_TransferSizeHigh: skip $01 ; $4306
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.0_DataBank: skip $01 ; $4307
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.0_TableAddrLow: skip $01 ; $4308
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.0_TableAddrHigh: skip $01 ; $4309
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.0_TransferLineNum: skip $01 ; $430A
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base $4310 ; Channel 1
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.1_TransferParameters: skip $01 ; $4310
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.1_DestinationAddr: skip $01 ; $4311
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.1_SourceAddrOffsetLow: skip $01 ; $4312
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.1_SourceAddrOffsetHigh: skip $01 ; $4313
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.1_SourceAddrBank: skip $01 ; $4314
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.1_TransferSizeLow: skip $01 ; $4315
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.1_TransferSizeHigh: skip $01 ; $4316
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.1_DataBank: skip $01 ; $4317
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.1_TableAddrLow: skip $01 ; $4318
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.1_TableAddrHigh: skip $01 ; $4319
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.1_TransferLineNum: skip $01 ; $431A
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base $4320 ; Channel 2
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.2_TransferParameters: skip $01 ; $4320
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.2_DestinationAddr: skip $01 ; $4321
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.2_SourceAddrOffsetLow: skip $01 ; $4322
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.2_SourceAddrOffsetHigh: skip $01 ; $4323
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.2_SourceAddrBank: skip $01 ; $4324
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.2_TransferSizeLow: skip $01 ; $4325
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.2_TransferSizeHigh: skip $01 ; $4326
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.2_DataBank: skip $01 ; $4327
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.2_TableAddrLow: skip $01 ; $4328
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.2_TableAddrHigh: skip $01 ; $4329
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.2_TransferLineNum: skip $01 ; $432A
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base $4330 ; Channel 3
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.3_TransferParameters: skip $01 ; $4330
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.3_DestinationAddr: skip $01 ; $4331
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.3_SourceAddrOffsetLow: skip $01 ; $4332
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.3_SourceAddrOffsetHigh: skip $01 ; $4333
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.3_SourceAddrBank: skip $01 ; $4334
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.3_TransferSizeLow: skip $01 ; $4335
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.3_TransferSizeHigh: skip $01 ; $4336
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.3_DataBank: skip $01 ; $4337
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.3_TableAddrLow: skip $01 ; $4338
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.3_TableAddrHigh: skip $01 ; $4339
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.3_TransferLineNum: skip $01 ; $433A
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base $4340 ; Channel 4
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.4_TransferParameters: skip $01 ; $4340
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.4_DestinationAddr: skip $01 ; $4341
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.4_SourceAddrOffsetLow: skip $01 ; $4342
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.4_SourceAddrOffsetHigh: skip $01 ; $4343
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.4_SourceAddrBank: skip $01 ; $4344
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.4_TransferSizeLow: skip $01 ; $4345
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.4_TransferSizeHigh: skip $01 ; $4346
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.4_DataBank: skip $01 ; $4347
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.4_TableAddrLow: skip $01 ; $4348
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.4_TableAddrHigh: skip $01 ; $4349
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.4_TransferLineNum: skip $01 ; $434A
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base $4350 ; Channel 5
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.5_TransferParameters: skip $01 ; $4350
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.5_DestinationAddr: skip $01 ; $4351
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.5_SourceAddrOffsetLow: skip $01 ; $4352
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.5_SourceAddrOffsetHigh: skip $01 ; $4353
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.5_SourceAddrBank: skip $01 ; $4354
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.5_TransferSizeLow: skip $01 ; $4355
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.5_TransferSizeHigh: skip $01 ; $4356
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.5_DataBank: skip $01 ; $4357
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.5_TableAddrLow: skip $01 ; $4358
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.5_TableAddrHigh: skip $01 ; $4359
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.5_TransferLineNum: skip $01 ; $435A
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base $4360 ; Channel 6
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.6_TransferParameters: skip $01 ; $4360
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.6_DestinationAddr: skip $01 ; $4361
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.6_SourceAddrOffsetLow: skip $01 ; $4362
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.6_SourceAddrOffsetHigh: skip $01 ; $4363
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.6_SourceAddrBank: skip $01 ; $4364
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.6_TransferSizeLow: skip $01 ; $4365
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.6_TransferSizeHigh: skip $01 ; $4366
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.6_DataBank: skip $01 ; $4367
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.6_TableAddrLow: skip $01 ; $4368
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.6_TableAddrHigh: skip $01 ; $4369
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.6_TransferLineNum: skip $01 ; $436A
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base $4370 ; Channel 7
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.7_TransferParameters: skip $01 ; $4370
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.7_DestinationAddr: skip $01 ; $4371
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.7_SourceAddrOffsetLow: skip $01 ; $4372
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.7_SourceAddrOffsetHigh: skip $01 ; $4373
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.7_SourceAddrBank: skip $01 ; $4374
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.7_TransferSizeLow: skip $01 ; $4375
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.7_TransferSizeHigh: skip $01 ; $4376
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.7_DataBank: skip $01 ; $4377
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.7_TableAddrLow: skip $01 ; $4378
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.7_TableAddrHigh: skip $01 ; $4379
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.7_TransferLineNum: skip $01 ; $437A
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}
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endstruct
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; ============================================================================== |